AV-51002
2015.12.16
1-74
HPS JTAG Timing Specifications
HPS JTAG Timing Specifications
Table 1-62: HPS JTAG Timing Parameters and Values for Arria V Devices
Symbol
Description
Min
30
14
14
2
Max
—
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
tJCP
tJCH
tJCL
TCK clock period
TCK clock high time
TCK clock low time
—
—
tJPSU (TDI)
tJPSU (TMS)
tJPH
TDI JTAG port setup time
TMS JTAG port setup time
JTAG port hold time
JTAG port clock to output
—
3
—
5
—
tJPCO
—
—
—
12(89)
14(89)
14(89)
tJPZX
JTAG port high impedance to valid output
JTAG port valid output to high impedance
tJPXZ
Configuration Specifications
This section provides configuration specifications and timing for Arria V devices.
POR Specifications
Table 1-63: Fast and Standard POR Delay Specification for Arria V Devices
POR Delay
Minimum
Maximum
12(90)
Unit
ms
Fast
4
Standard
100
300
ms
(89)
(90)
A 1-ns adder is required for each VCCIO _HPS voltage step down from 3.0 V. For example, tJPCO= 13 ns if VCCIO _HPS of the TDO I/O bank = 2.5 V, or
14 ns if it equals 1.8 V.
The maximum pulse width of the fast POR delay is 12 ms, providing enough time for the PCIe hard IP to initialize after the POR trip.
Arria V GX, GT, SX, and ST Device Datasheet
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