AV-51002
2015.12.16
2-23
Reference Clock
Unit
Transceiver Speed Grade 2
Transceiver Speed Grade 3
Symbol/Description
Conditions
Min
—
—
—
—
—
—
Typ
—
—
—
—
—
—
Max
-70
Min
—
—
—
—
—
—
Typ
—
—
—
—
—
—
Max
-70
100 Hz
1 kHz
dBc/Hz
-90
-90
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
ps (rms)
Transmitter REFCLK Phase
Noise (622 MHz) (140)
10 kHz
100 kHz
-100
-110
-120
3
-100
-110
-120
3
≥1 MHz
Transmitter REFCLK Phase
Jitter (100 MHz) (141)
10 kHz to 1.5 MHz
(PCIe)
RREF
—
—
1800 1%
—
—
1800 1%
—
Ω
Related Information
Arria V Device Overview
For more information about device ordering codes.
(140)
To calculate the REFCLK phase noise requirement at frequencies other than 622 MHz, use the following formula: REFCLK phase noise at f(MHz) =
REFCLK phase noise at 622 MHz + 20*log(f/622).
To calculate the REFCLK rms phase jitter requirement for PCIe at reference clock frequencies other than 100 MHz, use the following formula:
REFCLK rms phase jitter at f(MHz) = REFCLK rms phase jitter at 100 MHz × 100/f.
(141)
Arria V GZ Device Datasheet
Send Feedback
Altera Corporation
INTEL [ INTEL ]
