AV-51002
2015.12.16
2-21
Switching Characteristics
Switching Characteristics
Transceiver Performance Specifications
Reference Clock
Table 2-22: Reference Clock Specifications for Arria V GZ Devices
Speed grades shown refer to the PMA Speed Grade in the device ordering code. The maximum data rate could be restricted by the Core/PCS speed grade.
Contact your Altera Sales Representative for the maximum data rate specifications in each speed grade combination offered. For more information about
device ordering codes, refer to the Arria V Device Overview.
Transceiver Speed Grade 2
Transceiver Speed Grade 3
Symbol/Description
Conditions
Unit
Min Typ Max
Min Typ Max
Reference Clock
Dedicated reference clock 1.2-V PCML, 1.4-V PCML, 1.5-V PCML, 2.5-V PCML, Differential LVPECL, LVDS,
pin
and HCSL
Supported I/O Standards
RX reference clock pin
—
1.4-V PCML, 1.5-V PCML, 2.5-V PCML, LVPECL, and LVDS
Input Reference Clock
Frequency
40
—
710
40
—
710
710
MHz
MHz
(CMU PLL) (136)
Input Reference Clock
Frequency
—
100
—
710
100
—
(ATX PLL)(136)
Rise time
Fall time
Measure at 60 mV of
differential signal (137)
—
—
—
—
400
400
—
—
—
—
400
400
ps
Measure at 60 mV of
differential signal (137)
(136)
(137)
The input reference clock frequency options depend on the data rate and the device speed grade.
REFCLKperformance requires to meet transmitter REFCLKphase noise specification.
Arria V GZ Device Datasheet
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