Switching Characteristics
Page 17
Table 20. Transceiver Specifications for Arria V GX and SX Devices (Part 2 of 4)
Transceiver Speed Grade 4 Transceiver Speed Grade 6
Symbol/
Description
Conditions
Unit
Min
Typ
Max
Min
Typ
Max
Transceiver Clocks
PCIe
Receiver Detect
fixedclkclock frequency
—
75
125
—
—
—
75
125
—
—
MHz
MHz
Transceiver Reconfiguration
Controller IP
—
125
125
(mgmt_clk_clk) clock
frequency
Receiver
Supported I/O Standards
Data rate (14)
1.5 V PCML, 2.5 V PCML, LVPECL, and LVDS
—
—
611
—
6553.6
611
—
3125
1.2
Mbps
V
Absolute VMAX for a receiver
—
—
1.2
—
—
(5)
pin
Absolute VMIN for a receiver
pin
—
—
–0.4
—
—
—
—
–0.4
—
—
—
—
V
V
Maximum peak-to-peak
differential input voltage VID
(diff p-p) before device
configuration
1.6
1.6
Maximum peak-to-peak
differential input voltage VID
(diff p-p) after device
configuration
—
—
—
—
2.2
—
—
—
2.2
V
Minimum differential eye
opening at the receiver serial
—
—
85
—
—
—
85
—
—
—
mV
mV
(6)
input pins
650/800
650/800
VICM (AC coupled)
VICM (DC coupled)
(7)
(7)
≤ 3.2 Gbps (8)
85-Ωsetting
100-Ωsetting
120-Ωsetting
150-Ωsetting
—
670
—
—
—
—
—
4
700
85
730
—
—
—
—
10
—
—
—
670
—
—
—
—
—
4
700
85
730
—
—
—
—
10
—
—
—
mV
Ω
100
120
150
—
100
120
150
—
Ω
Differential on-chip
termination resistors
Ω
Ω
(9)
tLTR
µs
µs
µs
µs
(10)
tLTD
—
—
—
(11)
tLTD_manual
—
4
—
4
—
(12)
tLTR_LTD_manual
—
15
—
15
—
Programmable ppm detector
—
—
62.5, 100, 125, 200, 250, 300, 500, and 1000
200 200
ppm
UI
(13)
Run Length
—
—
—
—
December 2013 Altera Corporation
Arria V GX, GT, SX, and ST Device Datasheet
INTEL [ INTEL ]
