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5AGXFB3K6F31C5N 参数 Datasheet PDF下载

5AGXFB3K6F31C5N图片预览
型号: 5AGXFB3K6F31C5N
PDF下载: 下载PDF文件 查看货源
内容描述: [Field Programmable Gate Array, 622MHz, PBGA896, ROHS COMPLIANT, FBGA-896]
分类和应用: 可编程逻辑
文件页数/大小: 122 页 / 2566 K
品牌: INTEL [ INTEL ]
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Electrical Characteristics  
Page 15  
Table 18. Differential HSTL and HSUL I/O Standards for Arria V Devices  
VCCIO (V)  
Typ  
VDIF(DC) (V)  
VX(AC) (V)  
Typ  
VCM(DC) (V)  
Typ  
VDIF(AC) (V)  
I/O  
Standard  
Min  
Max  
Min  
Max  
Min  
Max  
Min  
Max  
Min  
Max  
HSTL-18  
Class I, II  
1.71  
1.8  
1.5  
1.2  
1.89  
0.2  
0.2  
0.78  
1.12  
0.78  
1.12  
0.4  
HSTL-15  
Class I, II  
1.425  
1.14  
1.575  
1.26  
0.68  
0.9  
0.68  
0.9  
0.4  
0.3  
HSTL-12  
Class I, II  
VCCIO  
+ 0.3  
0.5 x  
VCCIO  
0.4 x V 0.5 x V 0.6 x  
VCCIO  
VCCIO  
+ 0.48  
0.16  
CCIO  
CCIO  
0.5 x  
VCCIO  
+0.12  
0.5 x VCCIO 0.5 x  
– 0.12 VCCIO  
0.4 x V 0.5 x V 0.6 x  
VCCIO  
HSUL-12  
1.14  
1.2  
1.3  
0.26 0.26  
0.44  
0.44  
CCIO  
CCIO  
Table 19. Differential I/O Standard Specifications for Arria V Devices  
(2)  
(2), (7)  
VCCIO (V)  
VID (mV) (1)  
VICM(DC) (V)  
Condition  
VOD (V)  
VOCM (V)  
I/O Standard  
Min Typ Max Min Condition Max Min  
Max Min Typ Max Min Typ Max  
Transmitter, receiver, and input reference clock pins of high-speed transceivers use the PCML I/O standard. For  
PCML  
transmitter, receiver, and reference clock I/O pin specifications, refer to Table 20 and Table 21.  
DMAX  
1.25 Gbps  
0.05  
1.05  
0.25  
1.80  
1.55  
1.45  
2.5 V LVDS  
VCM  
1.25 V  
=
2.375 2.5 2.625 100  
0.247  
0.1  
0.6 1.125 1.25 1.375  
(3)  
DMAX  
>1.25 Gbps  
RSDS (HIO)  
VCM =  
1.25 V  
2.375 2.5 2.625 100  
2.375 2.5 2.625 200  
0.2 0.6  
0.5  
1
1.2  
1.2  
1.4  
1.4  
(4)  
Mini-LVDS  
(HIO) (5)  
600 0.300  
1.425 0.25  
0.6  
DMAX  
700 Mbps  
0.60  
1.80  
1.60  
LVPECL (6)  
2.375 2.5 2.625 300  
DMAX  
>700 Mbps  
1.00  
Notes to Table 19:  
(1) The minimum VID value is applicable over the entire common mode range, VCM  
.
(2) RL range: 90 RL 110 Ω.  
(3) For optimized LVDS receiver performance, the receiver voltage input range must be within 1.0V to 1.6V for data rates above 1.25 Gbps and 0 V to 1.85 V for  
data rates below 1.25 Gbps.  
(4) For optimized RSDS receiver performance, the receiver voltage input range must be within 0.25 V to 1.45 V.  
(5) For optimized Mini-LVDS receiver performance, the receiver voltage input range must be within 0.3 V to 1.425 V.  
(6) For optimized LVPECL receiver performance, the receiver voltage input range must be within 0.85 V to 1.75 V for data rates above 700 Mbps and 0.45 V to  
1.95 V for data rates below 700 Mbps.  
(7) This applies to default pre-emphasis setting only.  
December 2013 Altera Corporation  
Arria V GX, GT, SX, and ST Device Datasheet