Processor Configuration Registers
2.10.15 MBASE—Memory Base Address Register
This register controls the processor to PCI Express-G non-prefetchable memory access
routing based on the following formula:
MEMORY_BASE ≤ address ≤ MEMORY_LIMIT
The upper 12 bits of the register are read/write and correspond to the upper 12
address bits A[31:20] of the 32 bit address. The bottom 4 bits of this register are read-
only and return zeroes when read. This register must be initialized by the configuration
software. For the purpose of address decode, address bits A[19:0] are assumed to be
0. Thus, the bottom of the defined memory address range will be aligned to a 1 MB
boundary.
B/D/F/Type:
Address Offset:
Reset Value:
Access:
0/6/0/PCI
20–21h
FFF0h
RW
16 bits
0h
Size:
BIOS Optimal Default
Reset
Value
RST/
PWR
Bit
Access
Description
Memory Address Base (MBASE)
15:4
3:0
RW
RO
FFFh
0h
Uncore
This field corresponds to A[31:20] of the lower limit of the
memory range that will be passed to PCI Express-G.
Reserved (RSVD)
172
Datasheet, Volume 2
INTEL [ INTEL ]
