Features
Example: The Intel Xeon Processor E7-8800/4800/2800 Product Families processor
supports a maximum Intel SMI transfer rate of 6.4 GT/s. Therefore, offset 33h-34h has
a value of 6400h.
Offset:
33h-34h
Bit
Description
15:0
Maximum Intel SMI Transfer Rate
0000h-FFFFh: MHz
7.5.4.6
MINSMI: Minimum Intel SMI Transfer Rate
This listing provides the minimum “operating” Intel SMI transfer rate. Systems may
need to read this offset to decide if processors and Intel 7500 scalable memory buffer s
support the same Intel SMI Transfer Rate. The data provided is the transfer rate,
rounded to a whole number, and reflected in binary coded decimal. Writes to this
register have no effect.
Example: The Intel Xeon Processor E7-8800/4800/2800 Product Families processor
supports a minimum operating Intel SMI transfer rate of 4.8 GT/s. Therefore, offset
35h-36h has a hex value of 4800h.
Offset:
35h-36h
Bit
Description
15:0
Minimum Intel SMI Transfer Rate
0000h-FFFFh: MHz
7.5.4.7
VIOVID: VIO VID
Offset 37h-38h is the Processor VIO VID (Voltage Identification) field and contains the
voltage requested via the VID pins. This field, rounded to the next thousandth, is in mV
and is reflected in binary coded decimal. Some systems read this offset to determine if
all processors support the same default VID setting. Writes to this register have no
effect.
Example: A voltage of 1.350 V maximum core VID would contain 1350h in Offset 36-
37h.
Offset:
37h-38h
Bit
Description
15:0
VIO VID
0000h-FFFFh: mV
7.5.4.8
VIOVTH: VIO Voltage Tolerance, High
Offset 39h contains the VIO voltage tolerance, high. This is the maximum voltage
swing above the required voltage allowed. This field, rounded to the next thousandth,
is in mV and is reflected in binary coded decimal. A value of FF indicates that this value
is undetermined. Writes to this register have no effect.
Example: A 50 mV tolerance would be saved as 50h.
Datasheet Volume 1 of 2
161
INTEL [ INTEL ]
