Features
Offset:
21h-22h
Bit
Description
15:0
Maximum P0 Core Frequency
0000h-FFFFh: MHz
7.5.3.5
MAXVID: Maximum Core VID
This location contains the maximum Core VID (Voltage Identification) voltage that may
be requested via the VID pins. This field, rounded to the next thousandth, is in mV and
is reflected in binary coded decimal. Writes to this register have no effect.
Example: A voltage of 1.350 V maximum core VID would contain 1350h.
Offset:
23h-24h
Bit
Description
15:0
Maximum Core VID
0000h-FFFFh: mV
7.5.3.6
MINVID: Minimum Core VID
This location contains the Minimum Core VID (Voltage Identification) voltage that may
be requested via the VID pins. This field, rounded to the next thousandth, is in mV and
is reflected in binary coded decimal. Writes to this register have no effect.
Example: A voltage of 1.000 V maximum core VID would contain 1000h.
Offset:
25h-26h
Bit
Description
15:0
Maximum Core VID
0000h-FFFFh: mV
7.5.3.7
VTH: Core Voltage Tolerance, High
This location contains the maximum Core Voltage Tolerance DC offset high. This field,
rounded to the next thousandth, is in mV and is reflected in binary coded decimal.
Writes to this register have no effect. A value of FF indicates that this value is
undetermined. Writes to this register have no effect.
Example: 50 mV tolerance would be saved as 50h.
Offset:
27h
Bit
Description
7:0
Core Voltage Tolerance, High
00h-FFh: mV
158
Datasheet Volume 1 of 2
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