Features
Offset:
41h-42h
Bit
Description
15:0
L3 Cache Size
0000h-FFFFh: KB
7.5.4.13
CVID: Cache Voltage ID
This field contains the voltage requested via the CVID pins. This field is in mV and is
reflected in hex. Some systems read this offset to determine if all processors support
the same default CVID setting. Writes to this register have no effect.
Example: A voltage of 1.350 V CVID would contain an Offset 43-44h value of 1350h.
Offset:
43h-44h
Bit
Description
15:0
Cache Voltage ID
0000h-FFFFh: mV
7.5.4.14
CVTH: Cache Voltage Tolerance, High
This location contains the maximum Cache Voltage Tolerance DC offset high. This field,
rounded to the next thousandth, is in mV and is reflected in binary coded decimal. A
value of FF indicates that this value is undetermined. Writes to this register have no
effect.
Example: A 50 mV tolerance would be saved as 50h.
Offset:
45h
Bit
Description
7:0
Cache Voltage Tolerance, High
00h-FFh: mV
7.5.4.15
CVTL: Cache Voltage Tolerance, Low
This location contains the maximum Cache Voltage Tolerance DC offset low. This field,
rounded to the next thousandth, is in mV and is reflected in binary coded decimal. A
value of FF indicates that this value is undetermined. Writes to this register have no
effect.
Example: A 50 mV tolerance would be saved as 50h.
Offset:
46h
Bit
Description
7:0
Cache Voltage Tolerance, Low
00h-FFh: mV
Datasheet Volume 1 of 2
163
INTEL [ INTEL ]
