Signal Description
2.24
Power and Ground Signals
Table 2-24. Power and Ground Signals (Sheet 1 of 2)
Name
Description
Reference for 5 V tolerance on core well inputs. This power may be shut off in
S3, S4, S5 or G3 states.
V5REF
V5REF_Sus
Vcc1_1
Reference for 5 V tolerance on suspend well inputs. This power is not expected
to be shut off unless the system is unplugged.
1.1 V supply for core well logic. This power may be shut off in S3, S4, S5 or G3
states.
1.5 V supply for Logic and I/O. This power may be shut off in S3, S4, S5 or G3
states.
Vcc1_5_A
Vcc1_5_B
Vcc3_3
1.5 V supply for Logic and I/O. This power may be shut off in S3, S4, S5 or G3
states.
3.3 V supply for core well I/O buffers. This power may be shut off in S3, S4,
S5 or G3 states.
1.1V supply for Controller Link. This plane must be on in S0 and other times
Controller Link is used.
VccCL1_1
VccCL1_5
VccCL3_3
This voltage is generated internally (see Section 2.25.1 for strapping option)
and, this pin can be left as No Connect unless decoupling is required.
1.5V supply for Controller Link. This plane must be on in S0 and other times
Controller Link is used.
This voltage is generated internally (see Section 2.25.1 for strapping option),
and this pin can be left as No Connect unless decoupling is required.
3.3V supply for Controller Link. This is a separate power plane that may or
may not be powered in S3–S5 states. This plane must be on in S0 and other
times Controller Link is used.
NOTE: VccCL3_3 must always be powered when VccLAN3_3 is powered.
Power supply for DMI. 1.05V, 1.25V or 1.5V depending on (G)MCH’s DMI
voltage.
VccDMI
1.5 V supply for core well logic. This signal is used for the DMI PLL. This power
may be shut off in S3, S4, S5 or G3 states.
VccDMIPLL
VccGLAN1_5
VccGLAN3_3
VccGLANPLL
1.5V supply for integrated Gigabit LAN I/O buffers. This power is on in S0 and
is turned of in S3, S4, S5, even it integrated Gigabit LAN is not used.
3.3V supply for integrated Gigabit LAN logic and I/O. This power is on in S0
and is turned of in S3, S4, S5, even it integrated Gigabit LAN is not used.
1.5V supply for core well logic. This signal is used for the integrated Gigabit
LAN PLL. This power is shut off in S3, S4, S5 and G3 states.
Core supply for Intel High Definition Audio. This pin can be either 1.5 or 3.3 V.
This power may be shut off in S3, S4, S5 or G3 states.
NOTE: VccSusHDA and VccHDA can be connected to either 1.5 V or 3.3 V
supplies, but both pins must be connected to supplies that are the
same nominal value.
VccHDA
1.1 V supply for LAN controller logic. This is a separate power plane that may
or may not be powered in S3–S5 states.
VccLAN1_1
This voltage is generated internally (see Section 2.25.1 for strapping option)
and, these pins can be left as No Connect unless decoupling is required.
Datasheet
73
INTEL [ INTEL ]
