LPC Interface Bridge Registers (D31:F0)
13.1.23 GEN1_DEC—LPC I/F Generic Decode Range 1 Register
(LPC I/F—D31:F0)
Offset Address: 84h – 87h
Attribute:
Size:
Power Well:
R/W
32 bit
Core
Default Value:
00000000h
Bit
Description
31:24
Reserved
Generic I/O Decode Range Address[7:2] Mask — R/W. A 1 in any bit position
indicates that any value in the corresponding address bit in a received cycle will be
treated as a match. The corresponding bit in the Address field, below, is ignored. The
mask is only provided for the lower 6 bits of the DWord address, allowing for decoding
blocks up to 256 bytes in size.
23:18
17:16 Reserved
Generic I/O Decode Range 1 Base Address (GEN1_BASE) — R/W. This address is
15:2
aligned on a 128-byte boundary, and must have address lines 31:16 as 0.
NOTE: The ICH Does not provide decode down to the word or byte level.
1
0
Reserved
Generic Decode Range 1 Enable (GEN1_EN) — R/W.
0 = Disable.
1 = Enable the GEN1 I/O range to be forwarded to the LPC I/F.
13.1.24 GEN2_DEC—LPC I/F Generic Decode Range 2 Register
(LPC I/F—D31:F0)
Offset Address: 88h – 8Bh
Attribute:
Size:
Power Well:
R/W
32 bit
Core
Default Value:
00000000h
Bit
Description
31:24
Reserved
Generic I/O Decode Range Address[7:2] Mask — R/W. A 1 in any bit position
indicates that any value in the corresponding address bit in a received cycle will be
treated as a match. The corresponding bit in the Address field, below, is ignored. The
mask is only provided for the lower 6 bits of the DWord address, allowing for decoding
blocks up to 256 bytes in size.
23:18
17:16 Reserved
Generic I/O Decode Range 2 Base Address (GEN1_BASE) — R/W.
NOTE: The ICH Does not provide decode down to the word or byte level.
15:2
1
Reserved
Generic Decode Range 2 Enable (GEN2_EN) — R/W.
0
0 = Disable.
1 = Enable the GEN2 I/O range to be forwarded to the LPC I/F.
Datasheet
401
INTEL [ INTEL ]
