Functional Description
5.16.2
Theory of Operation
5.16.2.1
Standard ATA Emulation
The ICH10 contains a set of registers that shadow the contents of the legacy IDE
registers. The behavior of the Command and Control Block registers, PIO, and DMA
data transfers, resets, and interrupts are all emulated.
Note:
The ICH10 will assert INTR when the master device completes the EDD command
regardless of the command completion status of the slave device. If the master
completes EDD first, an INTR is generated and BSY will remain '1' until the slave
completes the command. If the slave completes EDD first, BSY will be '0' when the
master completes the EDD command and asserts INTR. Software must wait for busy to
clear (0) before completing an EDD command, as required by the ATA5 through ATA7
(T13) industry standards.
5.16.2.2
48-Bit LBA Operation
The SATA host controller supports 48-bit LBA through the host-to-device register FIS
when accesses are performed via writes to the task file. The SATA host controller will
ensure that the correct data is put into the correct byte of the host-to-device FIS.
There are special considerations when reading from the task file to support 48-bit LBA
operation. Software may need to read all 16-bits. Since the registers are only 8-bits
wide and act as a FIFO, a bit must be set in the device/control register, which is at
offset 3F6h for primary and 376h for secondary (or their native counterparts).
If software clears bit 7 of the control register before performing a read, the last item
written will be returned from the FIFO. If software sets bit 7 of the control register
before performing a read, the first item written will be returned from the FIFO.
5.16.3
SATA Swap Bay Support
The ICH10 provides for basic SATA swap bay support using the PSC register
configuration bits and power management flows. A device can be powered down by
software and the port can then be disabled, allowing removal and insertion of a new
device.
Note:
This SATA swap bay operation requires board hardware (implementation specific),
BIOS, and operating system support.
5.16.4
Hot Plug Operation
ICH10 supports Hot Plug Surprise removal and Insertion Notification in the PARTIAL,
SLUMBER and Listen Mode states when used with Low Power Device Presence
Detection. Software can take advantage of power savings in the low power states while
enabling hot plug operation. Refer to chapter 7 of the AHCI specification for details.
5.16.4.1
Low Power Device Presence Detection
Low Power Device Presence Detection enables SATA Link Power Management to co-
exist with hot plug (insertion and removal) without interlock switch or cold presence
detect. The detection mechanism allows Hot Plug events to be detectable by hardware
across all link power states (Active, PARTIAL, SLUMBER) as well as AHCI Listen Mode.
If the Low Power Device Presence Detection circuit is disabled the ICH10 reverts to Hot
Plug Surprise Removal Notification (without an interlock switch) mode that is mutually
exclusive of the PARTIAL and SLUMBER power management states.
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Datasheet
INTEL [ INTEL ]
