Functional Description
The following waveform shows a 1-byte serial write with a data byte of 5Ah. The
internal clock and bit position are for reference purposes only. The Manchester D is the
resultant data generated and serialized onto the GPIO. Since the buffer is operating in
open-drain mode the transitions are from high-Z to 0 and back.
Bit
7 6 5 4 3 2 1 0
Internal Clock
Manchester D
8-bit sync field
(1111_1110)
2 clk
idle
5A data byte
5.15.6
Intel Management Engine GPIOs
The following GPIOs can be used as Controller Link GPIOs: GPIO9/WOL_EN, GPIO10/
CPU_MISSING/JTAGTMS (Corporate Only), GPIO24/MEM_LED, and GPIO57/TPM_PP/
JTAGTCK (Corporate Only). Controller Link GPIOs are only available on Intel AMT or
ASF enabled platforms with supporting Intel Management Engine firmware. Controller
Link GPIOs are owned by the Intel Management Engine and are configured by Intel
Management Engine firmware. When configured a a Controller Link GPIO the
GPIO_USE_SEL bit is ignored. If the Controller Link GPIO is utilized in a platform, its
associated GPIO functionality is no longer available to the host. If the Controller Link
GPIO is not utilized in a platform, the signal can instead be used as its associated
General Purpose I/O.
5.16
SATA Host Controller (D31:F2, F5)
The SATA function in the ICH10 has three modes of operation to support different
operating system conditions. In the case of Native IDE enabled operating systems, the
ICH10 utilizes two controllers to enable all six ports of the bus. The first controller
(Device 31: Function 2) supports ports 0–3 and the second controller (Device 31:
Function 5) supports ports 4 and 5. When using a legacy operating system, only one
controller (Device 31: Function 2) is available that supports ports 0 - 3. In AHCI or
RAID mode, only one controller (Device 31: Function 2) is used enabling all six ports.
The MAP register, Section 15.1.29, provides the ability to share PCI functions. When
sharing is enabled, all decode of I/O is done through the SATA registers. Device 31,
Function 1 (IDE controller) is hidden by software writing to the Function Disable
Register (D31, F0, offset F2h, bit 1), and its configuration registers are not used.
The ICH10 SATA controllers feature six sets of interface signals (ports) that can be
independently enabled or disabled (they cannot be tri-stated or driven low). Each
interface is supported by an independent DMA controller.
The ICH10 SATA controllers interact with an attached mass storage device through a
register interface that is equivalent to that presented by a traditional IDE host adapter.
The host software follows existing standards and conventions when accessing the
register interface and follows standard command protocol conventions.
Note:
SATA interface transfer rates are independent of UDMA mode settings. SATA interface
transfer rates will operate at the bus’s maximum speed, regardless of the UDMA mode
reported by the SATA device or the system BIOS.
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Datasheet
INTEL [ INTEL ]
