Functional Description
A simplified hardware/software register interface provides control and status
information to track the activity of this block. Software enabling the serial blink
capability should implement an algorithm referenced below to send the serialized
message on the enabled GPIO.
1. Read the Go/Busy status bit in the GP_SB_CMDSTS register and verify it is cleared.
This will ensure that the GPIO is idled and a previously requested message is still
not in progress.
2. Write the data to serialize into the GP_SB_DATA register (Section 13.10.7).
3. Write the DLS and DRS values into the GP_SB_CMDSTS register and set the Go bit.
This may be accomplished using a single write.
The reference diagram shows the LEDs being powered from the suspend supply. By
providing a generic capability that can be used both in the main and the suspend power
planes maximum flexibility can be achieved. A key point to make is that the ICH will not
unintentionally drive the LED control pin low unless a serialization is in progress.
System board connections utilizing this serialization capability are required to use the
same power plane controlling the LED as the ICH10 GPIO pin. Otherwise, the ICH10
GPIO may float low during the message and prevent the LED from being controlled
from the SIO. The hardware will only be serializing messages when the core power well
is powered and the processor is operational.
Care should be taken to prevent the ICH10 from driving an active ‘1’ on a pin sharing
the serial LED capability. Since the SIO could be driving the line to 0, having the ICH
drive a 1 would create a high current path. A recommendation to avoid this condition
involves choosing a GPIO defaulting to an input. The GP_SER_BLINK register
(Section 13.10.7) should be set first before changing the direction of the pin to an
output. This sequence ensures the open-drain capability of the buffer is properly
configured before enabling the pin as an output.
5.15.5.2
Serial Message Format
In order to serialize the data onto the GPIO, an initial state of high-Z is assumed. The
SIO is required to have its LED control pin in a high-Z state as well to allow ICH10 to
blink the LED (refer to the reference diagram).
The three components of the serial message include the sync, data, and idle fields. The
sync field is 7 bits of ‘1’ data followed by 1 bit of ‘0’ data. Starting from the high-Z state
(LED on) provides external hardware a known initial condition and a known pattern. In
case one or more of the leading 1 sync bits are lost, the 1s followed by 0 provide a
clear indication of ‘end of sync’. This pattern will be used to ‘lock’ external sampling
logic to the encoded clock.
The data field is shifted out with the highest byte first (MSB). Within each byte, the
most significant bit is shifted first (MSb).
The idle field is enforced by the hardware and is at least 2 bit times long. The hardware
will not clear the Busy and Go bits until this idle time is met. Supporting the idle time in
hardware prevents time-based counting in BIOS as the hardware is immediately ready
for the next serial code when the Go bit is cleared. Note that the idle state is
represented as a high-Z condition on the pin. If the last transmitted bit is a 1, returning
to the idle state will result in a final 0-1 transition on the output Manchester data. Two
full bit times of idle correspond to a count of 4 time intervals (the width of the time
interval is controlled by the DRS field).
Datasheet
175
INTEL [ INTEL ]
