Functional Description
This ensures that only BIOS can change the GPIO configuration. If the GLE bit is
cleared by unauthorized software, BIOS will set the GLE bit again when the SMI# is
triggered and these registers will continue to be locked down.
5.15.5
Serial POST Codes Over GPIO
ICH10 adds the extended capability allowing system software to serialize POST or other
messages on GPIO. This capability negates the requirement for dedicated diagnostic
LEDs on the platform. Additionally, based on the newer BTX form factors, the PCI bus
as a target for POST codes is increasingly difficult to support as the total number of PCI
devices supported are decreasing.
5.15.5.1
Theory of operation
For the ICH10 generation POST code serialization logic will be shared with GPIO. These
GPIOs will likely be shared with LED control offered by the Super I/O (SIO) component.
The following reference diagram shows a likely configuration.
Figure 5-9. Serial Post over GPIO Reference Circuit
V_3P3_STBY
R
ICH
SIO
LED
Note: The pull-up value is based on the brightness required.
The anticipated usage model is that either the ICH10 or the SIO can drive a pin low to
turn off an LED. In the case of the power LED, the SIO would normally leave its
corresponding pin in a high-Z state to allow the LED to turn on. In this state, the ICH10
can blink the LED by driving its corresponding pin low and subsequently tri-stating the
buffer.
An external optical sensing device can detect the on/off state of the LED. By externally
post-processing the information from the optical device, the serial bit stream can be
recovered. The hardware will supply a ‘sync’ byte before the actual data transmission
to allow external detection of the transmit frequency. The frequency of transmission
should be limited to 1 transition every 1μs to ensure the detector can reliably sample
the on/off state of the LED. To allow flexibility in pull-up resistor values for power
optimization, the frequency of the transmission is programmable via the DRS field in
the GP_SB_CMDSTS register (Section 13.10.6).
The serial bit stream is Manchester encoded. This choice of transmission ensures that a
transition will be seen on every clock. The 1 or 0 data is based on the transmission
happening during the high or low phase of the clock.
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Datasheet
INTEL [ INTEL ]
