Functional Description
5.15
General Purpose I/O (D31:F0)
The ICH10 contains up to 61 General Purpose Input/Output (GPIO) signals. Each GPIO
can be configured as an input or output signal. The number of inputs and outputs
varies depending on ICH10 configuration.
5.15.1
Power Wells
Some GPIOs exist in the suspend power plane. Care must be taken to make sure GPIO
signals are not driven high into powered-down planes. Some ICH10 GPIOs may be
connected to pins on devices that exist in the core well. If these GPIOs are outputs,
there is a danger that a loss of core power (PWROK low) or a Power Button Override
event results in the ICH10 driving a pin to a logic 1 to another device that is powered
down.
5.15.2
5.15.3
SMI# and SCI Routing
The routing bits for GPIO[0:15] allow an input to be routed to SMI# or SCI, or neither.
Note that a bit can be routed to either an SMI# or an SCI, but not both.
Triggering
GPIO[1:15] have “sticky” bits on the input. Refer to the GPE0_STS register. As long as
the signal goes active for at least 2 clock cycles, the ICH10 keeps the sticky status bit
active. The active level can be selected in the GP_LVL register. If the system is in an S0
or an S1 state, the GPI inputs are sampled at 33 MHz, so the signal only needs to be
active for about 60 ns to be latched. In the S3–S5 states, the GPI inputs are sampled at
32.768 kHz, and thus must be active for at least 61 microseconds to be latched. If the
input signal is still active when the latch is cleared, it will again be set. Another edge
trigger is not required. This makes these signals “level” triggered inputs.
5.15.4
GPIO Registers Lockdown
The following GPIO registers are locked down when the GPIO Lockdown Enable (GLE)
bit is set. The GLE bit resides in D31:F0:GPIO Control (GC) register.
• Offset 00h: GPIO_USE_SEL
• Offset 04h: GP_IO_SEL
• Offset 0Ch: GP_LVL
• Offset 30h: GPIO_USE_SEL2
• Offset 34h: GPI_IO_SEL2
• Offset 38h: GP_LVL2
• Offset 40h: GPIO_USE_SEL3 (Corporate Only)
• Offset 44h: GPI_IO_SEL3 (Corporate Only)
• Offset 48h: GP_LVL3 (Corporate Only)
• Offset 60h: GP_RST_SEL
Once these registers are locked down, they become Read-Only registers and any
software writes to these registers will have no effect. To unlock the registers, the GPIO
Lockdown Enable (GLE) bit is required to be cleared to ‘0’. When the GLE bit changes
from a ‘1’ to a ‘0’ a System Management Interrupt (SMI#) is generated if enabled.
Once the GPIO_UNLOCK_SMI bit is set, it can not be changed until a PLTRST# occurs.
Datasheet
173
INTEL [ INTEL ]
