10.2.39VCSTS—VC0 Resource Status Register.................................................... 137
10.2.40VC0CAP—VC0 Resource Capability Register.............................................. 137
10.2.41VC1CTL—VC1 Resource Control Register ................................................. 138
10.2.42VC1STS—VC1 Resource Status Register .................................................. 138
10.2.43RCCAP—Root Complex Link Declaration Enhanced
Capability Header Register..................................................................... 139
10.2.44ESD—Element Self Description Register................................................... 139
10.2.45L1DESC—Link 1 Description Register....................................................... 140
10.2.46L1ADD—Link 1 Address Register............................................................. 140
10.3 Memory Mapped Configuration Registers ............................................................ 141
10.3.1 GCAP—Global Capabilities Register ......................................................... 144
10.3.2 VMIN—Minor Version Register................................................................ 144
10.3.3 VMAJ—Major Version Register................................................................ 144
10.3.4 OUTPAY—Output Payload Capability Register ........................................... 145
10.3.5 INPAY—Input Payload Capability Register ................................................ 145
10.3.6 GCTL—Global Control Register ............................................................... 146
10.3.7 STATESTS - State Change Status ........................................................... 147
10.3.8 GSTS—Global Status Register ................................................................ 149
10.3.9 ECAP—Extended Capabilities.................................................................. 150
10.3.10STRMPAY—Stream Payload Capability ..................................................... 150
10.3.11INTCTL—Interrupt Control Register......................................................... 151
10.3.12INTSTS—Interrupt Status Register.......................................................... 152
10.3.13WALCLK—Wall Clock Counter Register..................................................... 153
10.3.14SSYNC—Stream Synchronization Register................................................ 153
10.3.15CORBBASE—CORB Base Address Register................................................ 153
10.3.16CORBWP—CORB Write Pointer Register ................................................... 154
10.3.17CORBRP—CORB Read Pointer Register .................................................... 154
10.3.18CORBCTL—CORB Control Register .......................................................... 155
10.3.19CORBST—CORB Status Register ............................................................. 155
10.3.20CORBSIZE—CORB Size Register ............................................................. 155
10.3.21RIRBBASE—RIRB Base Address Register.................................................. 156
10.3.22RIRBWP—RIRB Write Pointer Register ..................................................... 156
10.3.23RINTCNT—Response Interrupt Count Register.......................................... 157
10.3.24RIRBCTL—RIRB Control Register ............................................................ 157
10.3.25RIRBSTS—RIRB Status Register ............................................................. 158
10.3.26RIRBSIZE—RIRB Size Register ............................................................... 158
10.3.27IC—Immediate Command Register ......................................................... 159
10.3.28IR—Immediate Response Register .......................................................... 159
10.3.29IRS—Immediate Command Status Register.............................................. 160
10.3.30DPBASE—DMA Position Base Address Register.......................................... 160
10.3.31SDCTL—Stream Descriptor Control Register............................................. 161
10.3.32SDSTS—Stream Descriptor Status Register.............................................. 163
10.3.33SDLPIB—Stream Descriptor Link Position in Buffer Register........................ 164
10.3.34SDCBL—Stream Descriptor Cyclic Buffer Length Register........................... 164
10.3.35SDLVI—Stream Descriptor Last Valid Index Register ................................. 165
10.3.36SDFIFOW—Stream Descriptor FIFO Watermark Register............................ 165
10.3.37SDFIFOS—Stream Descriptor FIFO Size Register....................................... 166
10.3.38SDFMT—Stream Descriptor Format Register............................................. 167
10.3.39SDBDPL—Stream Descriptor Buffer Descriptor Pointer List Base Register ..... 168
10.4 Vendor Specific Memory Mapped Registers ......................................................... 169
10.4.1 EM1—Extended Mode 1 Register............................................................. 169
10.4.2 INRC—Input Stream Repeat Count Register............................................. 170
10.4.3 OUTRC—Output Stream Repeat Count Register ........................................ 170
10.4.4 FIFOTRK – FIFO Tracking Register .......................................................... 171
10.4.5 SDPIB—Stream DMA Position in Buffer Register........................................ 171
Datasheet
7
INTEL [ INTEL ]
