5.3
System Memory Map..........................................................................................60
5.3.1 Legacy Video Area (A0000h – BFFFFh).......................................................62
5.3.2 Expansion Area (C0000h – DFFFFh) ..........................................................62
5.3.3 Extended System BIOS Area (E0000h – EFFFFh).........................................62
5.3.4 System BIOS Area (F0000h – FFFFFh).......................................................62
5.3.5 EHCI Controller Area...............................................................................62
5.3.6 Programmable Attribute Map (PAM)...........................................................62
5.3.7 Top of Memory Segment (TSEG)...............................................................63
5.3.8 APIC Configuration Space (FEC00000h – FECFFFFFh)...................................63
5.3.9 High BIOS Area ......................................................................................63
5.3.10 Boot Block Update ..................................................................................63
5.3.11 Memory Shadowing.................................................................................64
5.3.12 Locked Transactions................................................................................64
I/O Address Space.............................................................................................65
5.4.1 Fixed I/O Decode Ranges.........................................................................65
5.4.2 Variable I/O Decode Ranges.....................................................................66
I/O Mapped Registers.........................................................................................67
5.5.1 NSC—NMI Status and Control Register ......................................................67
5.5.2 NMIE—NMI Enable Register......................................................................67
5.5.3 CONFIG_ADDRESS—Configuration Address Register....................................68
5.5.4 RSTC—Reset Control Register...................................................................69
5.5.5 CONFIG_DATA—Configuration Data Register ..............................................69
5.4
5.5
6
General Chipset Configuration..................................................................................71
6.1
Root Complex Capability.....................................................................................71
6.1.1 RCTCL—Root Complex Topology Capabilities List.........................................72
6.1.2 ESD—Element Self Description .................................................................72
6.1.3 HDD—Intel® HD Audio Description ...........................................................73
6.1.4 HDBA—Intel® HD Audio Base Address.......................................................73
Interrupt Pin and Routing Configuration................................................................74
6.2.1 Interrupt Pin Configuration.......................................................................74
6.2.2 Interrupt Route Configuration...................................................................77
General Configuration Register ............................................................................80
6.3.1 RC—RTC Configuration Register................................................................80
6.2
6.3
7
Host Bridge (D0:F0).................................................................................................81
7.1
Functional Description ........................................................................................81
7.1.1 Dynamic Bus Inversion............................................................................81
7.1.2 FSB Interrupt Overview ...........................................................................81
7.1.3 CPU BIST Strap ......................................................................................82
Host PCI Configuration Registers..........................................................................82
7.2.1 VID—Identification Register .....................................................................82
7.2.2 DID—Identification Register .....................................................................83
7.2.3 PCICMD—PCI Command Register..............................................................83
7.2.4 PCISTS—PCI Status Register....................................................................83
7.2.5 RID—Revision Identification Register.........................................................83
7.2.6 CC—Class Code Register..........................................................................84
7.2.7 SS—Subsystem Identifiers Register...........................................................84
7.2.8 Miscellaneous (Port 05h)..........................................................................88
7.2
8
Memory Controller (D0:F0) ......................................................................................89
8.1
Functional Overview...........................................................................................89
8.1.1 DRAM Frequencies and Data Rates............................................................89
8.1.2 DRAM Command Scheduling ....................................................................89
8.1.3 Page Management ..................................................................................89
4
Datasheet
INTEL [ INTEL ]
