8.2
DRAM Technologies and Organization................................................................... 90
8.2.1 DRAM Address Mapping........................................................................... 90
DRAM Clock Generation...................................................................................... 92
DDR2 On-Die Termination .................................................................................. 92
DRAM Power Management.................................................................................. 92
8.5.1 CKE Powerdown..................................................................................... 92
8.5.2 Interface High-Impedance....................................................................... 92
8.5.3 Refresh................................................................................................. 93
8.5.4 Self-Refresh .......................................................................................... 93
8.5.5 Dynamic Self-Refresh ............................................................................. 93
8.5.6 DDR2 Voltage........................................................................................ 93
8.3
8.4
8.5
9
Graphics, Video, and Display (D2:F0) ...................................................................... 95
9.1
Graphics Overview ............................................................................................ 95
9.1.1 3-D Core Key Features............................................................................ 95
9.1.2 Shading Engine Key Features................................................................... 95
9.1.3 Vertex Processing................................................................................... 96
9.1.4 Pixel Processing ..................................................................................... 97
9.1.5 Unified Shader....................................................................................... 97
9.1.6 Multi Level Cache ................................................................................... 98
Video Decode Overview...................................................................................... 98
9.2.1 Entropy Coding ...................................................................................... 99
9.2.2 Motion Compensation ............................................................................. 99
9.2.3 Deblocking .......................................................................................... 100
9.2.4 Output Reference Frame Storage Format................................................. 100
Display Overview ............................................................................................ 101
9.3.1 Planes ................................................................................................ 101
9.3.2 Display Pipes ....................................................................................... 102
9.3.3 Display Ports ....................................................................................... 102
Configuration Registers.................................................................................... 104
9.4.1 VID—Vendor Identification Register ........................................................ 105
9.4.2 DID—Device Identification Register......................................................... 105
9.4.3 PCICMD—PCI Command Register ........................................................... 105
9.4.4 PCISTS—PCI Status Register.................................................................. 106
9.4.5 RID—Revision Identification................................................................... 106
9.4.6 CC—Class Codes Register...................................................................... 106
9.4.7 HEADTYP—Header Type Register............................................................ 107
9.4.8 MEM_BASE—Memory Mapped Base Address Register ................................ 107
9.4.9 IO_BASE—I/O Base Address Register...................................................... 107
9.4.10 GMEM_BASE—Graphics Memory Base Address Register............................. 108
9.4.11 GTT_BASE—Graphics Translation Table Base Address Register ................... 108
9.4.12 SS—Subsystem Identifiers..................................................................... 109
9.4.13 CAP_PTR—Capabilities Pointer Register ................................................... 109
9.4.14 INT_LN—Interrupt Line Register............................................................. 109
9.4.15 INT_PN—Interrupt Pin Register .............................................................. 109
9.4.16 GC—Graphics Control Register ............................................................... 110
9.4.17 SSRW—Software Scratch Read/Write Register.......................................... 110
9.4.18 BSM—Base of Stolen Memory Register .................................................... 111
9.4.19 MSAC—Multi Size Aperture Control ......................................................... 111
9.4.20 MSI_CAPID—MSI Capability Register....................................................... 112
9.4.21 NXT_PTR3—Next Item Pointer #3 Register .............................................. 112
9.4.22 MSI_CTL—Message Control Register ....................................................... 112
9.4.23 MSI_ADR—Message Address Register ..................................................... 113
9.4.24 MSI_DATA—Message Data Register ........................................................ 113
9.4.25 VEND_CAPID—Vendor Capability Register................................................ 113
9.2
9.3
9.4
Datasheet
5
INTEL [ INTEL ]
