14.4.5 INT_CTRL—Interrupt Control Register ..................................................... 287
14.4.6 DEV_CTRL—Device Control Register........................................................ 288
14.5 Device Endpoint Register Map........................................................................... 290
14.5.1 EPnIB—Endpoint [0..3] Input Base Address Register ................................. 290
14.5.2 EPnIL—Endpoint [0,1] Input Length Register............................................ 290
14.5.3 EPnIPB—Endpoint [0..3] Input Position in Buffer Register .......................... 291
14.5.4 EPnIDL—Endpoint [0..3] Input Descriptor in List Register .......................... 291
14.5.5 EPnITQ—Endpoint [0..3] Input Transfer in Queue Register......................... 291
14.5.6 EPnIMPS—Endpoint [0..3] Input Maximum Packet Size Register.................. 292
14.5.7 EPnIS—Endpoint [0..3] Input Status Register........................................... 292
14.5.8 EPnIC—Endpoint [0..3] Input Configuration Register................................. 293
14.5.9 EPnOB—Endpoint [0..3] Output Base Address Register.............................. 294
14.5.10EPnOL—Endpoint [0..3] Output Length Register ....................................... 295
14.5.11EPnOPB—Endpoint [0..3] Output Position in Buffer Register ....................... 295
14.5.12EPnODL—Endpoint [0..3] Output Descriptor in List Register ....................... 295
14.5.13EPnOTQ—Endpoint [0..3] Output Transfer in Queue Register...................... 296
14.5.14EPnOMPS—Endpoint [0..3] Output Maximum Packet Size Register .............. 296
14.5.15EPnOS—Endpoint [0..3] Output Status Register........................................ 297
14.5.16EPnOC—Endpoint [0..3] Output Configuration Register.............................. 297
14.5.17EPnOSPS—Endpoint [0..3] Output Setup Package Status Register............... 299
14.5.18EPnOSP—Endpoint [0..3] Output Setup Packet Register............................. 299
15
SDIO/MMC (D30:F0, F1, F2).................................................................................. 301
15.1 SDIO Functional Description (D30:F0, F1, F2) ..................................................... 301
15.1.1 Protocol Overview ................................................................................ 301
15.1.2 Integrated Pull-Up Resistors .................................................................. 302
15.2 PCI Configuration Registers .............................................................................. 303
15.2.1 VID—Vendor Identification Register ........................................................ 303
15.2.2 DID—Device Identification Register......................................................... 304
15.2.3 PCICMD—PCI Command Register ........................................................... 304
15.2.4 PCISTS—PCI Status Register.................................................................. 305
15.2.5 CC—Class Codes Register...................................................................... 305
15.2.6 HEADTYP—Header Type Register............................................................ 306
15.2.7 MEM_BASE—Base Address Register ........................................................ 306
15.2.8 SS—Subsystem Identifier Register.......................................................... 306
15.2.9 INT_LN—Interrupt Line Register............................................................. 307
15.2.10INT_PN—Interrupt Pin Register .............................................................. 307
15.2.11SLOTINF—Slot Information Register........................................................ 307
15.2.12BC—Buffer Control Register ................................................................... 308
15.2.13SDIOID—SDIO Identification Register ..................................................... 309
15.2.14CAPCNTL—SDIO Capability Control Register............................................. 309
15.2.15MANID—Manufacturer ID ...................................................................... 310
15.2.16FD—Function Disable Register................................................................ 310
15.3 SDIO/MMC Memory-Mapped Registers ............................................................... 311
15.3.1 DMAADR—DMA Address Register............................................................ 312
15.3.2 BLKSZ—Block Size Register ................................................................... 313
15.3.3 BLKCNT—Block Count Register............................................................... 314
15.3.4 CMDARG—Command Argument Register ................................................. 314
15.3.5 XFRMODE—Transfer Mode Register......................................................... 315
15.3.6 XFRMODE—Transfer Mode Register......................................................... 316
15.3.7 CMD—Command Register...................................................................... 317
15.3.8 RESP—Response Register...................................................................... 318
15.3.9 BUFDATA—Buffer Data Register ............................................................. 318
15.3.10PSTATE—Present State Register............................................................. 318
15.3.11HOSTCTL—Host Control Register ............................................................ 321
Datasheet
11
INTEL [ INTEL ]
