54 Counter Operating Modes........................................................................................ 366
55 I/O Register Map.................................................................................................... 368
56 Legacy Timer Interrupt Mapping............................................................................... 374
57 Master 8259 Input Mapping..................................................................................... 379
58 Slave 8259 Input Mapping....................................................................................... 379
59 Content of Interrupt Vector Byte.............................................................................. 380
60 8259 I/O Register Mapping...................................................................................... 385
61 Interrupt Delivery Address Value.............................................................................. 393
62 Interrupt Delivery Data Value .................................................................................. 393
63 APIC Memory-Mapped Register Locations .................................................................. 394
64 IDX Register Values................................................................................................ 394
65 Serial Interrupt Mode Selection................................................................................ 398
66 Data Frame Format................................................................................................ 399
67 RTC I/O Registers .................................................................................................. 401
68 RTC (Standard) RAM Bank....................................................................................... 401
69 GPIO I/O Register Map ........................................................................................... 406
70 SMBus Timings...................................................................................................... 411
71 SMBus I/O Register Map ......................................................................................... 412
72 Intel® SCH Absolute Maximum Ratings..................................................................... 417
73 Intel® SCH Maximum Power Consumption ................................................................ 418
74 Intel® SCH Buffer Types......................................................................................... 419
75 Intel® SCH Signal Group Definitions......................................................................... 420
76 Thermal Design Power............................................................................................ 421
77 DC Current Characteristics ...................................................................................... 421
78 Operating Condition Power Supply and Reference DC Characteristics............................. 423
79 Active Signal DC Characteristics............................................................................... 424
80 PLL Noise Rejection Specifications ............................................................................ 427
81 Intel® SCH Pin List Arranged by Signal Name............................................................ 439
Datasheet
17
INTEL [ INTEL ]
