Tables
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8
9
PCI Devices and Functions.........................................................................................23
Intel® SCH Buffer Types ...........................................................................................27
Functional Strap Definitions .......................................................................................46
Reset State Definitions..............................................................................................47
Intel® SCH Reset State.............................................................................................48
Intel® SCH Integrated Termination Resistors...............................................................53
Intel® SCH Clock Domains ........................................................................................55
Register Access Types and Definitions .........................................................................57
PCI Devices and Functions.........................................................................................59
10 Intel® SCH Memory Map...........................................................................................60
11 Programmable Attribute Map......................................................................................62
12 Fixed I/O Decode Ranges ..........................................................................................65
13 Variable I/O Decode Ranges.......................................................................................66
14 Root Complex Configuration Registers.........................................................................71
15 Interrupt Pin Field Bit Decoding..................................................................................74
16 Interrupt Pin Register Map.........................................................................................74
17 Interrupt Route Field Bit Decoding ..............................................................................77
18 Interrupt Route Register Map.....................................................................................77
19 Host Bridge Configuration Register Address Map...........................................................82
20 DRAM Attributes.......................................................................................................90
21 DRAM Address Decoder.............................................................................................91
22 Hardware-Accelerated Video Codec Support.................................................................98
23 Pixel Format for the Luma (Y) Plane..........................................................................100
24 Pixel Formats for the Cr/Cb (V/U) Plane.....................................................................100
25 Graphics and Video PCI Configuration Register Address Map.........................................104
26 Intel HD Audio PCI Configuration Registers ................................................................122
27 Intel HD Audio Memory Mapped Configuration Registers ..............................................141
28 MSI vs. PCI IRQ Actions ..........................................................................................173
29 PCI Express* Register Address Map ..........................................................................175
30 Bits Maintained in Low Power States .........................................................................204
31 UHCI Controller PCI Register Address Map (D29:F0/F1/F2) ..........................................205
32 USB I/O Registers ..................................................................................................211
33 Run/Stop, Debug Bit Interaction SWDBG (Bit 5), Run/Stop (Bit 0) Operation..................214
34 UHCI vs. EHCI .......................................................................................................223
35 USB EHCI PCI Register Address Map .........................................................................230
36 EHCI Capability Registers ........................................................................................247
37 Enhanced Host Controller Operational Register Address Map.........................................250
38 Debug Port Register Address Map .............................................................................263
39 USB Client Controller PCI Register Address Map (D26:F0) ............................................273
40 USB Client I/O Registers..........................................................................................282
41 Determining the Response Type ...............................................................................301
42 Response Register Mapping .....................................................................................302
43 SDIO/MMC PCI Register Address Map........................................................................303
44 SDIO/MMC Memory-Mapped Register Address Map .....................................................311
45 Supported PATA Standards and Modes ......................................................................339
46 ATA Command Block Registers (PATA_DCS1#)...........................................................340
47 ATA Control Block Registers (PATA_DCS3#)...............................................................340
48 PRD Base Address ..................................................................................................342
49 PRD Descriptor Information .....................................................................................342
50 Interrupt/Active Bit Interaction.................................................................................343
51 PATA Register Address Map .....................................................................................345
52 PATA Memory-Mapped I/O Register Address Map........................................................351
53 LPC Interface PCI Register Address Map ....................................................................354
16
Datasheet
INTEL [ INTEL ]
