Revision History
Revision
Number
Description
Revision Date
-001
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Initial Release
April 2008
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Updated Reference Documents
Chapter 1.3.2 – Added support of 2GB of memory and of 2048Mb devices
Chapter 2.1 – Corrected CMOS/AGTL+ assignments
Chapter 2.5 – Added that PCIe compensation pins also act for LVDS and SDVO interfaces
Chapter 2.10 – Clarified that SMB_ALERT# does not wake the system or generate an interrupt
Chapter 2.11 – Clarified that RTCRST# does not clear CMOS
Chapter 2.14 – Clarified that the Intel® SCH will not de-assert CLKREQ#
Chapter 3.1 – Corrected reset states for CLKREQ# (VOX-known), RSMRST# (VLI), and LVDS
(VOH)
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Chapter 5.3 – Added support of up to 2GB of memory
Chapter 8.2 – Added 2048 Mbit device support
Chapter 9.3.2 – Removed assertion that display PLLs can be disabled
Chapter 9.4.2 – Updated Device ID Register
Chapter 11.1.4 – Added section asserting that No Snoop is not supported
Chapter 11.2.15 – Corrected default value
Chapter 12.2.16 – Corrected Bit[1:0] definitions
Chapter 15.2.8 – Removed CRID description - wrong place
Chapter 15.3.10 – Corrected Bit 10 definition
Chapter 17.1 – Clarified that the Intel® SCH does not support LPC DMA
Chapter 17.5.1 – Corrected Bit[15:12] definitions
Chapter 18.7.2 – Corrected CGIO default value
-002
March 2009
Chapter 20.2 – Added I
, I
and I
and corrected I
parameter
VCC33RTC VCC5REF
VCC5REFSUS
VCCPCIEBG
description
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1.3.2 - Added support of x8 memory device width
2.17 - Updated functional straps configuration for 266 MHz Gfx in Table 3
5.4.1 - Changed PATA port disable to "NO" in Table 12
8.2 - Add x8-width devices to Tables 20 and 21
9.2 - Add 1080p @ 24fps to the codecs supporting 1080i in Table 22
9.3.2 - Corrected bottom of pixel clocks range
9.4.34 - Changed Bits [1:0] for 266 MHz Gfx support
10.3.7 - Removed WAKEEN register
11.2.27 - Disclosed Bit 8 (CLKREQ# Enabled) with instruction
12.1.4 - Removed support of USB Legacy Keyboard
12.2.16 - Clarified USB_RES is in the Resume well
13.1.5 - Removed support of USB Legacy Keyboard
13.3.1.3 - Clarified HCSPARAMS is in the Suspend well
16.2 - Corrected offsets for D0TIM and D1TIM in Table 52
18 - Corrected Chapter title
18.6.7.2 - Clarified that RTC_REGB is in the Resume well and reset by RSMRST#
18.7.2 - Corrected RGIO default value in Table 70
18.7.3.1 - Corrected RGEN default value
-003
May 2010
20.1 - Moved TDO to CMOS Open Drain in Table 76
20.2 - Adjusted TDP range to include US15X in Table 77
20.2 - Added second spec to ISUS_VCCSM, corrected IVCC33RTC, and added US15X core
current in Table 78
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20.3 - Corrected CMOS and CMOS_OD VIL(max) and VIH(min), and added VIL,LVM and
VIH,LVM to CMOS_HDA in Table 80
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18
Datasheet
INTEL [ INTEL ]
