15.3.12PWRCTL—Power Control Register............................................................321
15.3.13BLKGAPCTL—Block Gap Control Register..................................................322
15.3.14WAKECTL—Wake Control Register...........................................................323
15.3.15CLKCTL—Clock Control Register..............................................................324
15.3.16TOCTL—Timeout Control Register............................................................325
15.3.17SWRST—Software Reset Register............................................................326
15.3.18NINTSTS—Normal Interrupt Status Register.............................................327
15.3.19ERINTSTS—Error Interrupt Status Register ..............................................329
15.3.20NINTEN—Normal Interrupt Enable Register ..............................................330
15.3.21ERINTEN—Error Interrupt Enable Register................................................331
15.3.22NINTSIGEN—Normal Interrupt Signal Enable Register................................332
15.3.23ERINTSIGEN—Error Interrupt Signal Enable Register .................................333
15.3.24AC12ERRSTS—Automatic CMD12 Error Status Register..............................334
15.3.25CAP—Capabilities Register .....................................................................334
15.3.26MCCAP—Maximum Current Capabilities Register .......................................336
15.3.27SLTINTSTS—Slot Interrupt Status Register...............................................336
15.3.28HCVER—Host Controller Version Register .................................................336
16
Parallel ATA (D31:F1) ............................................................................................339
16.1 Functional Overview.........................................................................................339
16.1.1 Programmed I/O Transfers.....................................................................339
16.1.2 Multi-Word DMA Transfers .....................................................................342
16.1.3 Synchronous (Ultra) DMA Transfers.........................................................344
16.2 PCI Configuration Registers...............................................................................345
16.2.1 ID—Identifiers Register .........................................................................346
16.2.2 PCICMD—Command Register..................................................................346
16.2.3 PCISTS—Device Status Register .............................................................346
16.2.4 RID—Revision ID Register......................................................................347
16.2.5 CC—Class Code Register........................................................................347
16.2.6 CLS—Cache Line Size Register................................................................347
16.2.7 MLT—Master Latency Timer Register .......................................................347
16.2.8 BMBAR—Bus Master Base Address Register..............................................348
16.2.9 SS—Sub System Identifiers Register .......................................................348
16.2.10INTR—Interrupt Information Register ......................................................348
16.2.11MC—Miscellaneous Configuration Register................................................349
16.2.12D0TIM/D1TIM—Device 0/1 Timing Register ..............................................349
16.3 I/O Registers ..................................................................................................351
16.3.1 PCMD—Primary Command Register.........................................................351
16.3.2 PSTS—Primary Status Register...............................................................352
16.3.3 PDTP—Primary Descriptor Table Pointer Register.......................................352
17
LPC Interface (D31:F0)..........................................................................................353
17.1 Functional Overview.........................................................................................353
17.1.1 Memory Cycle Notes .............................................................................353
17.1.2 TPM 1.2 Support...................................................................................353
17.1.3 FWH Cycle Notes ..................................................................................353
17.1.4 LPC Output Clocks ................................................................................354
17.2 PCI Configuration Registers...............................................................................354
17.2.1 VID—Vendor Identification Register.........................................................355
17.2.2 DID—Device Identification Register.........................................................355
17.2.3 PCICMD—PCI COMMAND Register ...........................................................355
17.2.4 PCISTS—PCI Status Register..................................................................355
17.2.5 RID—Revision Identification Register.......................................................356
17.2.6 CC—Class Codes Register ......................................................................356
17.2.7 HEADTYP—Header Type Register ............................................................356
17.2.8 SS—Sub System Identifiers Register .......................................................357
12
Datasheet
INTEL [ INTEL ]
