Intel® HD Audio (D27:F0)
10.3
Memory Mapped Configuration Registers
The base memory location for these memory mapped configuration registers is
specified in the LBAR and UBAR registers (D27:F0:offset 10h and D27:F0:offset 14h).
The individual registers are then accessible at LBAR + Offset as indicated in Table 27.
These memory mapped registers must be accessed in byte, word, or Dword quantities.
Table 27.
Intel HD Audio Memory Mapped Configuration Registers (Sheet 1 of 3)
LBAR +
Mnemonic
Register Name
Default
Access
Offset
00h–01h
GCAP
Global Capabilities
4401h
RO
02h
VMIN
Minor Version
00h
RO
RO
RO
RO
03h
VMAJ
Major Version
01h
04h–05h
06h–07h
08h–0Bh
0Ch
OUTPAY
INPAY
Output Payload Capability
Input Payload Capability
Global Control
003Ch
001Dh
GCTL
00000000h R/W
WAKEEN
STATESTS
GSTS
Wake Enable
0000h
0000h
0000h
0030h
0018h
R/W, RO
0Eh
State Change Status
Global Status
R/W, RO
R/WC
RO
10h–11h
18h–19h
1Ah–1Bh
20h–23h
24h–27h
30h–33h
38h–3Bh
40h–43h
48h–49h
4Ah–4Bh
4Ch
OUTSTRMPAY Output Stream Payload Capability
INSTRMPAY
INTCTL
Input Stream Payload Capability
Interrupt Control
Interrupt Status
RO
00000000h R/W, RO
00000000h RO
INTSTS
WALCLK
SSYNC
Wall Clock Counter
Stream Synchronization
CORB Base Address
CORB Write Pointer
CORB Read Pointer
CORB Control
00000000h RO
00000000h R/W, RO
00000000h R/W, RO
CORBBASE
CORBWP
CORBRP
CORBCTL
CORBST
CORBSIZE
RIRBBASE
RIRBWP
RINTCNT
RIRBCTL
0000h
0000h
00h
R/W, RO
R/W, RO
R/W, RO
R/WC
4Dh
CORB Status
00h
4Eh
CORB Size
42h
RO
50h–53h
58h–59h
5Ah–5Bh
5Ch
RIRB Base Address
RIRB Write Pointer
Response Interrupt Count
RIRB Control
00000000h R/W, RO
0000h
0000h
00h
WO, RO
R/W, RO
R/W, RO
R/WC,
RO
5Dh
RIRBSTS
RIRB Status
00h
40h
5Eh
RIRBSIZE
RIRB Size
RO
60h–63h
64h–67h
IC
IR
Immediate Command
Immediate Response
00000000h R/W
00000000h RO
R/W, R/
WC, RO
68h–69h
IRS
Immediate Command Status
0000h
Datasheet
141
INTEL [ INTEL ]
