Intel® HD Audio (D27:F0)
10.2.41 VC1CTL—VC1 Resource Control Register
Address Offset:
Default Value:
120h–123h
00000000h
Attribute:
Size:
R/W, RO
32 bits
Default
Bit
and
Description
Access
VC1 Enable
0 = VC1 is disabled
1 = VC1 is enabled
0
R/W
31
NOTE: This bit is not reset on D3HOT to D0 transition.
0h
RO
30:27
26:24
23:8
Reserved
VC1 ID: This field assigns a VC ID to the VC1 resource. This field is not
used by the Intel® SCH hardware, but it is R/W to avoid confusing
software.
000b
R/W
0h
RO
Reserved
TC/VC Map: This field indicates the TCs that are mapped to the VC1
resource. Bit 0 is hardwired to 0 indicating that it cannot be mapped to
VC1. Bits [7:1] are implemented as R/W bits. This field is not used by the
Intel® SCH, but it is R/W to avoid confusing software.
00h
R/W, RO
7:0
10.2.42 VC1STS—VC1 Resource Status Register
Address Offset:
Default Value:
126h-127h
0000h
Attribute:
Size:
RO
16 Bits
Default
Bit
and
Description
Access
0
RO
15:0
Reserved
138
Datasheet
INTEL [ INTEL ]
