Intel® HD Audio (D27:F0)
10.2.7
CLS—Cache Line Size Register
Address Offset:
Default Value:
0Ch
00h
Attribute:
Size:
R/W
8 bits
Default
Bit
and
Description
Access
Cache Line Size (CLS): Does not apply to PCI Express. The PCI Express
specification requires this to be implemented as a R/W register but has no
functional impact on the Intel® SCH.
00h
R/W
7:0
10.2.8
10.2.9
LT—Latency Timer Register
Address Offset:
Default Value:
0Dh
00h
Attribute:
Size:
RO
8 bits
Default
Bit
and
Description
Access
00h
RO
7:0
Latency Timer: Hardwired to 00
HEADTYP—Header Type Register
Address Offset:
Default Value:
0Eh
00h
Attribute:
Size:
RO
8 bits
Default
Bit
and
Description
Access
00h
RO
7:0
Header Type: Hardwired to 00.
126
Datasheet
INTEL [ INTEL ]
