Graphics, Video, and Display (D2:F0)
9.4.23
MSI_ADR—Message Address Register
Register Address:
Default Value:
94-97h
00000000h
Attribute:
Size:
RO, R/W
32 bits
A read from this register produces undefined results.
Default
Bit
and
Description
Access
0
R/W
Address (ADDR): Lower 32-bits of the system specified message
address, always DWord aligned.
31:2
1:0
00b
RO
Reserved
9.4.24
MSI_DATA—Message Data Register
Register Address:
Default Value:
98-99h
0000h
Attribute:
Size:
RO, R/W
16 bits
Default
Bit
and
Description
Access
Data (DATA): This 16-bit field is programmed by system software and is
driven onto the lower word of data during the data phase of the MSI write
transaction.
0000h
R/W
15:0
9.4.25
9.4.26
VEND_CAPID—Vendor Capability Register
Register Address:
Default Value:
B0h
09h
Attribute:
Size:
RO
8 bits
Default
Bit
and
Description
Access
09h
RO
7:0
Capability ID (ID): 09h indicates a vendor-specific capability.
NXT_PTR2—Next Item Pointer #2 Register
Register Address:
Default Value:
B1h
90h/00h
Attribute:
Size:
RO
8 bits
Default
Bit
and
Description
Access
Pointer to Next Capability (NEXT): 90h indicates the address of the
next capability.
90h/00h
RO
7:0
However, if the FD.MD bit is set, the MSI capability will be disabled and
this register will report 00h indicating the Power Management capability is
the last capability in the list.
Datasheet
113
INTEL [ INTEL ]
