GMCH Register Description
4.4.2
Bridge Related Configuration Accesses
Configuration accesses on PCI Express or DMI are PCI Express Configuration TLPs.
•
•
•
Bus Number [7:0] is Header Byte 8 [7:0]
Device Number [4:0] is Header Byte 9 [7:3]
Function Number [2:0] is Header Byte 9 [2:0]
And special fields for this type of TLP:
•
•
Extended Register Number [3:0] is Header Byte 10 [3:0]
Register Number [5:0] is Header Byte 11 [7:2]
See the PCI Express specification for more information on both the PCI 2.3 compatible
and PCI Express Enhanced Configuration Mechanism and transaction rules.
4.4.2.1
PCI Express* Configuration Accesses
When the Bus Number of a type 1 Standard PCI Configuration cycle or PCI Express
Enhanced Configuration access matches the Device 1 Secondary Bus Number a PCI
Express Type 0 Configuration TLP is generated on the PCI Express link targeting the
device directly on the opposite side of the link. This should be Device 0 on the bus
number assigned to the PCI Express link (likely Bus 1).
The device on other side of link must be Device 0. The GMCH will Master Abort any
Type 0 Configuration access to a non-zero Device number. If there is to be more than
one device on that side of the link there must be a bridge implemented in the
downstream device.
When the Bus Number of a type 1 Standard PCI Configuration cycle or PCI Express
Enhanced Configuration access is within the claimed range (between the upper bound
of the bridge device’s Subordinate Bus Number register and the lower bound of the
bridge device’s Secondary Bus Number register) but doesn't match the Device 1
Secondary Bus Number, a PCI Express Type 1 Configuration TLP is generated on the
secondary side of the PCI Express link.
PCI Express Configuration Writes:
•
Internally the host interface unit will translate writes to PCI Express extended
configuration space to configuration writes on the backbone.
•
Writes to extended space are posted on the FSB, but non-posted on the PCI
Express or DMI (i.e., translated to configuration writes)
4.4.2.2
DMI Configuration Accesses
Accesses to disabled GMCH internal devices, bus numbers not claimed by the Host-PCI
Express bridge, or PCI Bus #0 devices not part of the GMCH will subtractively decode
to the ICH8 and consequently be forwarded over the DMI via a PCI Express
configuration TLP.
If the Bus Number is zero, the GMCH will generate a Type 0 Configuration Cycle TLP
on DMI. If the Bus Number is non-zero, and falls outside the range claimed by the
Datasheet
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