System Address Map
the extended SMRAM space is enabled, processor accesses to the TSEG range without
SMM attribute or without WB attribute are also forwarded to memory as invalid
accesses (see Table 3-5). Non-SMM-mode Write Back cycles that target TSEG space
are completed to DRAM for cache coherency. When SMM is enabled the maximum
amount of memory available to the system is equal to the amount of physical DRAM
minus the value in the TSEG register which is fixed at 1 MB, 2 MB or 8 MB.
3.2.3
Pre-allocated Memory
Voids of physical addresses that are not accessible as general system memory and
reside within system memory address range (< TOLUD) are created for SMM-mode
and legacy VGA graphics compatibility. It is the responsibility of BIOS to properly
initialize these regions. The following table details the location and attributes of the
regions. Enabling/Disabling these ranges are described in the GMCH Control Register
Device 0 (GCC).
Table 3-5. Pre-allocated Memory Example for 64 MB DRAM, 1-MB VGA and 1-MB TSEG
Memory Segments
Attributes
Comments
0000_0000h –
03DF_FFFFh
R/W
Available System Memory 62 MB
03E0_0000h –
03EF_FFFFh
SMM Mode Only -
processor Reads
TSEG Address Range & Pre-allocated
Memory
03F0_0000h –
03FF_FFFFh
R/W
Pre-allocated Graphics VGA memory.
1 MB (or 4/8/16/32/64 MB) when IGD is
enabled.
3.3
PCI Memory Address Range (TOLUD – 4GB)
This address range, from the top of low usable DRAM (TOLUD) to 4 GB is normally
mapped to the DMI Interface.
With PCI Express* port, there are two exceptions to this rule.
•
Addresses decoded to the PCI Express Memory Window defined by the MBASE1,
MLIMIT1, registers are mapped to PCI Express .
Note: AGP Aperture no longer exists with PCI Express.
In a Manageability Engine configuration, there are exceptions to this rule.
•
Addresses decoded to the ME Keyboard and Text MMIO range (EPKTBAR)
There are other MMIO Bars that may be mapped to this range or to the range above
TOUUD.
There are sub-ranges within the PCI Memory address range defined as APIC
Configuration Space, FSB Interrupt Space, and High BIOS Address Range. The
exceptions listed above for internal graphics and the PCI Express ports MUST NOT
overlap with these ranges.
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Datasheet
INTEL [ INTEL ]
