System Address Map
Figure 3-3. Main Memory Address Range
FFFF_FFFFh
4GB Max
FLASH
APIC
LT
Contains:
Dev 0, 1, 2, 3, 7
BARS
PCI Memory Range
& ICH/PCI ranges
TOLUD
IGD (1-64MB, optional)
TSEG (1MB/2MB/8MB, optional)
Main Memory
0100_0000h
00F0_0000h
16MB
15MB
ISA Hole (optional)
Main Memory
0010_0000h
0h
1MB
0MB
DOS Compatibility Memory
3.2.1
ISA Hole (15MB-16MB)
A hole can be created at 15 MB–16 MB as controlled by the fixed hole enable in Device
0 space. Accesses within this hole are forwarded to the DMI Interface. The range of
physical DRAM memory disabled by opening the hole is not remapped to the top of the
memory – that physical DRAM space is not accessible. This 15 MB – 16 MB hole is an
optionally enabled ISA hole.
Video accelerators originally used this hole. It is also used by validation and customer
SV teams for some of their test cards. That is why it is being supported. There is no
inherent BIOS request for the 15 MB – 16 MB window.
3.2.2
TSEG
TSEG is optionally 1 MB, 2 MB, or 8 MB in size. TSEG is below IGD stolen memory,
which is at the top of Low Usable physical memory (TOLUD). SMM-mode processor
accesses to enabled TSEG access the physical DRAM at the same address. Non-
processor originated accesses are not allowed to SMM space. PCI-Express, DMI, and
Internal Graphics originated cycle to enabled SMM space are handled as invalid cycle
type with reads and writes to location 0 and byte enables turned off for writes. When
Datasheet
51
INTEL [ INTEL ]
