Integrated Graphics Device Registers (D2:F0,F1)
8.2.19
MGGC—Mirror of Dev 0 GMCH Graphics Control Register
B/D/F/Type:
Address Offset:
Default Value:
Access:
0/2/1/PCI
52–53h
0030h
RO
Size:
16 bits
Bit
15:7
6:4
Access &
Description
Default
RO
00h
Reserved
RO
011b
Graphics Mode Select (GMS). This field is used to select the amount
of Main Memory that is pre-allocated to support the Internal Graphics
device in VGA (non-linear) and Native (linear) modes. The BIOS
ensures that memory is pre-allocated only when Internal graphics is
enabled.
000 = No memory pre-allocated. Device 2 (IGD) does not claim VGA
cycles (Mem and IO), and the Sub-Class Code field within
Device 2 function 0 Class Code register is 80.
001 = DVMT (UMA) mode, 1 MB of memory pre-allocated for frame
buffer.
010 = Reserved
011 = DVMT (UMA) mode, 8 MB of memory pre-allocated for frame
buffer.
100 = Reserved
101 = Reserved
110 = Reserved
111 = Reserved
Note: This register is locked and becomes Read Only when the D_LCK
bit in the
SMRAM register is set.
Reserved
3:2
1
RO
00b
IGD VGA Disable (IVD):
RO
0b
0 = Enable. Device 2 (IGD) claims VGA memory and I/O cycles, the
Sub-Class Code within Device 2 Class Code register is 00.
1 = Disable. Device 2 (IGD) does not claim VGA cycles (Memory and
I/O), and the Sub- Class Code field within Device 2, function 0
Class Code register is 80h.
0
Reserved
RO
0b
Datasheet
259
INTEL [ INTEL ]
