Integrated Graphics Device Registers (D2:F0,F1)
8.2.24
GDRST—Mirror of Dev2 Func0 Graphics Reset
B/D/F/Type:
Address Offset:
Default Value:
Access:
0/2/1/PCI
C0h
00h
RO
8 bits
Size:
This register is a mirror of the Graphics Reset Register in Device 2.
Bit
Access &
Default
Description
7:2
RO
0h
Reserved
Graphics Reset Status (GRS):
1
0
RO
0b
0 = Graphics subsystem not in Reset.
1 = Graphics Subsystem in Reset as a result of Graphics Reset.
Graphics Reset (GDR):
RO
0b
0 = De-assert display and render domain reset
1 = Assert display and render domain reset
8.2.25
PMCAPID—Mirror of Fun 0 Power Management
Capabilities ID
B/D/F/Type:
Address Offset:
Default Value:
Access:
0/2/1/PCI
D0–D1h
0001h
RO
Size:
16 bits
This register is a mirror of function 0 with the same R/W attributes. The hardware
implements a single physical register common to both functions 0 and 1.
Bit
Access &
Default
Description
15:8
RO
00h
Next Capability Pointer (NEXT_PTR): This contains a pointer to
next item in capabilities list. This is the final capability in the list and
must be set to 00h.
7:0
RO
Capability Identifier (CAP_ID): SIG defines this ID is 01h for power
01h
management.
Datasheet
263
INTEL [ INTEL ]
