Integrated Graphics Device Registers (D2:F0,F1)
8.1.9
HDR2—Header Type
B/D/F/Type:
Address Offset:
Default Value:
Access:
0/2/0/PCI
0Eh
80h
RO
8 bits
Size:
This register contains the Header Type of the IGD.
Bit
Access &
Default
Description
7
RO
1b
Multi Function Status (MFUNC): Indicates if the device is a Multi-
Function Device. The Value of this register is determined by Device 0,
offset 54h, DEVEN[4]. If Device 0 DEVEN[4] is set, the MFUNC bit is
also set.
6:0
RO
00h
Header Code (H): This is a 7-bit value that indicates the Header
Code for the IGD. This code has the value 00h, indicating a type 0
configuration space format.
8.1.10
GMADR—Graphics Memory Range Address
B/D/F/Type:
Address Offset:
Default Value:
Access:
0/2/0/PCI
18–1Fh
00000008h
RW, RO, RW/L
64 bits
Size:
IGD graphics memory base address is specified in this register.
Bit
Access &
Default
Description
63:36
35:29
RO
Reserved
RW
Memory Base Address (MBA): Set by the OS, these bits correspond
000b
to address signals 35:29.
28
RW/L
0b
512 MB Address Mask (512ADMSK): This Bit is either part of the
Memory Base Address (R/W) or part of the Address Mask (RO),
depending on the value of MSAC[1:0]. See MSAC (D2:F0, offset 62h)
for details.
27
RW/L
0b
256 MB Address Mask (256ADMSK): This bit is either part of the
Memory Base Address (R/W) or part of the Address Mask (RO),
depending on the value of MSAC[1:0]. See MSAC (D2:F0, offset 62h)
for details.
26:4
3
RO
000000h
Address Mask (ADM): Hardwired to 0s to indicate at least 128 MB
address range.
RO
1b
Prefetchable Memory (PREFMEM): Hardwired to 1 to enable
prefetching.
2:1
RO
00b
Memory Type (MEMTYP):
0 = 32-bit address.
1 = 64-bit address
0
RO
0b
Memory/IO Space (MIOS): Hardwired to 0 to indicate memory
space.
Datasheet
231
INTEL [ INTEL ]
