Errata
1.
Problem:
Implication:
PCI Express* Related Status Register Bits which Drive SERR
Generation Logic are Never Automatically Cleared
PCI Express* Port related status register bits which drive the SERR generation logic are
never automatically cleared. This includes being sticky through warm reset.
Follow-on (any after first occurrence) errors of same type are ignored because
associated status bit is not cleared.
Workaround:
BIOS Workaround available. Contact your Intel Field Representative for the latest BIOS
information.
Status:
NoFix. For affected steppings see the
Summary Table of Changes.
2.
Problem:
PCIEXBAR Decode Fails When Using Size=64MB or 128 MB and
MCHBAR is Not Aligned to 256MB
When accesses are to Device 0 and 1 on the configuration bus using the enhanced
configuration mechanism and the size is set to 64MB and the address is aligned to a
128M or 64M boundary, the transaction gets decoded as a type 1 transaction on the
backbone instead of the configuration bus.
May cause failure to boot or may lead to a system hang.
Fixed. For affected steppings, see the
Summary Table of Changes.
Implication:
Status:
Workaround:
Set the length to 64 MB or 128 MB and align it to a 256 MB boundary.
3.
Problem:
Implication:
PCI Express* SKP/InitFCx Contention
During PCI Express initialization, if a SKP is being transmitted immediately before an
InitFCx DLLP, then a partial InitFCx may be transmitted.
A slight delay (less than 100 ns) may occur during link initialization. Device may report
correctable error. InitFCx will automatically be repeated.
NoFix. For affected steppings, see the
Summary Table of Changes.
Workaround:
None.
Status:
4.
Problem:
Packet Dropped When Replay Timer Expires and Replay is in Progress
When a packet replay is in progress on the PCI Express* Port, and if some but not all of
the packets to be replayed are acknowledged and the replay timer expires on the same
clock cycle as the replay start of the first unacknowledged packet, the next packet in
the replay buffer may be sent with an old sequence number. That packet is seen by
receiver side as a duplicate and subsequently dropped.
Note:
This has only been reproduced in a synthetic test environment with heavy
error injection.
A fatal error may be registered by the MCH and the system may hang.
NoFix. For affected steppings, see the
Summary Table of Changes.
Implication:
Status:
Workaround:
None.
Intel® 3000 and 3010 Chipset Memory Controller Hub (MCH)
Specification Update
Order Number: 313954-004
9
INTEL [ INTEL CORPORATION ]
