13.
Relaxed Ordering Queue
Problem:
The 3000, 3010 MCH may experience an internal race condition between the host and
PCI Express internal clocks and may experience a hang when the following conditions
are met simultaneously:
1) When using a PCI Express endpoint (connected to MCH) that is generating at least
12 outstanding read requests to memory, with at least one of those requests setting
the Relaxed Ordering attribute
2) The CPU generates a downstream write burst (including a non-posted) to the PCI
Express endpoint that stalls due to lack of PCI Express posted credits
3) The MCH allows the Relaxed Order read completion to pass the posted memory write
Note: This has only been found in a synthetic testing environment.
Implication: System may exhibit a hang with either of the three failing signatures:
1) MCH doesn’t respond with completion to PCI Express-mem read (read completes on
DDR2 I/F)
2) MCH responds with 2 completions (instead of 1) with duplicate tags in response to
PCI Express-mem read (read also completes on DDR2 I/F)
3) CPU to PEG downstream write completes on FSB but never gets requested on PEG
Workaround: Refer to the 3000/3010 BIOS Spec Update
Status:
No Fix.
14.
Excessive Clock Jitter Observed on Intel® 3000 and 3010 Chipset
Memory Controller Hub (MCH) Reference Design Platforms. Not
Applicable to the Intel® 82945GZ GMCH and Intel® 82945PL MCH.
Problem:
DDR2-667 system memory clocks outperform the tCL/tCH spec of 48/52 by reaching
49/51, but do not meet the below listed JEDEC balloted DDR2-667 DRAM Device jitter
values at all times.
The jitter limits were measured at about the 9-sigma level.
Parameter
JEDEC
Value
(G)MCH
Value
tJIT(per)
125
250
125
175
225
250
250
290
470
150
350
450
545
600
tJIT(cc)
tJIT(duty)
tERR(2per)
tERR(3per)
tERR(4per)
tERR(5per)
Implication: None. Intel has characterized the system memory clocks and system timing margins
and shared the data with the major DRAM suppliers. Intel has determined and the
Order Number: 313954-004
12
Intel® 3000 and 3010 Chipset Memory Controller Hub (MCH)
Specifiication Update
INTEL [ INTEL ]
