major DRAM suppliers agree that this system clock errata should not cause memory-
clock functionality or timing related issues providing all other DRAM related interface
timing specifications are fulfilled according to DDR2 Intel specification addendum and
JEDEC DDR2 DRAM specification, and the Intel® 3000 and 3010 Chipset Memory
Controller Hub Platform Design Guide.
Workaround: None.
Status: NoFix. For affected steppings, see the Summary Table of Changes.
Intel® 3000 and 3010 Chipset Memory Controller Hub (MCH)
Specification Update
Order Number: 313954-004
13