Errata
Number
1
2
3
4
5
6
7
8
9
10
11
12
13
14
X
X
X
X
X
X
X
X
X
X
X
x
Steppings
A0
X
Status
NoFix
Fixed
NoFix
NoFix
NoFix
NoFix
NoFix
NoFix
NoFix
NoFix
NoFix
NoFix
NoFix
No Fix
ERRATA
PCI Express* related status register bits which drive SERR generation logic
are never automatically cleared.
PCIEXBAR Decode Fails When Using Size=64MB or 128 MB and MCHBAR is
Not Aligned to 256 MB.
PCI Express SKP/InitFCx Contention.
Packet Dropped When Replay Timer Expires and Replay is in Progress.
LOCK to non-DRAM Memory Flag (Register C8, Bit 9) is Getting Asserted
The PCI Express* Port Does Not Send The Correct TLP Type Downstream
When There is a Memory Read Request-Locked TLP.
PCI Express* Port Skip Sequence is Not Transmitted When Entering Recovery
State.
STPCLK# Throttling May Cause System to Hang
The Transaction Layer Resets the Completion Timer Counter before Receiving
a Passing CRC from the Link Layer on the PCI Express* Port.
Malformed Upstream IO or Configuration Write Cycles Are Not Being
Detected As Malformed on PCI Express* Port.
PCI Express* Port is Recognizing an Invalid Transaction with a CRC Error
from an Agent as Completed with CRS Status
PCI Express* Port Flow Control Updates Being Sent in During PM_REQ_ACK
Stream.
Relaxed Ordering Queue
Excessive Clock Jitter Observed on Intel® 3000 and 3010 Chipset Memory
Controller Hub (MCH) Reference Design Platforms.
Not Applicable to the
Intel® 82945GZ GMCH and Intel® 82945PL MCH
Specification Changes
Number
1
SPECIFICATION CHANGES
There are no Specification Changes in this Specification Update revision.
Specification Clarifications
No.
1
SPECIFICATION CLARIFICATIONS
There are no Specification Changes in this Specification Update revision.
Documentation Changes
No.
1
DOCUMENTATION CHANGES
Intel® 3000 and 3010 Chipset Memory Controller Hub (MCH)
Specification Update
Order Number: 313954-004
7
INTEL [ INTEL CORPORATION ]
