Status:
9.
NoFix. For affected steppings, see the Summary Table of Changes.
The Transaction Layer Resets the Completion Timer Counter before
Receiving a Passing CRC from the Link Layer on the PCI Express* Port
Problem:
The PCI Express* Port is resetting the completion timer before receiving a Transaction
Layer Packet (TLP) with a passing Cyclic Redundancy Check (CRC) indicator from the
Link Layer. The completion timer should only be resetting when there is a passing CRC
indicator from the Link Layer.
Note: This has only been reproduced in a synthetic test environment.
Implication: None known.
Workaround: None.
Status:
NoFix. For affected steppings, see the Summary Table of Changes.
10.
Malformed Upstream IO or Configuration Write Cycles Are Not Being
Detected As Malformed on PCI Express* Port
Problem:
Malformed upstream I/O or configuration write cycles are not being properly detected.
The I/O or configuration write cycles are put in the upstream non-posted queue as an
invalid cycle and an unsupported request completion is returned instead of a fatal error.
Note: This has only been reproduced in a synthetic test environment.
Implication: None. PCI Express* 1.0a compliant devices are not allowed to send I/O or
Configuration cycles upstream.
Workaround: None.
Status:
NoFix. For affected steppings, see the Summary Table of Changes.
11.
PCI Express* Port is Recognizing an Invalid Transaction with a CRC
Error from an Agent as Completed with CRS Status
Problem:
If the MCH has a downstream I/O cycle or memory read outstanding, and receives for
that cycle a completion TLP that has been corrupted in such a way that the status is
“Configuration Retry” (which is illegal), and another corruption within the same TLP
appears as a premature “END” symbol, then the MCH may violate system ordering
rules.
Note: This has only been reproduced in a synthetic simulation test environment
with heavy error injection.
Implication: Anomalous system behavior could result if the exact scenario described above occurs.
Workaround: None.
Status:
NoFix. For affected steppings, see the Summary Table of Changes.
12.
PCI Express* Port Flow Control Updates Being Sent in During
PM_REQ_ACK Stream
Problem:
A flow control update DLLP may be sent in the middle of continuous PM_REQ_ACK
packets while entering L2/L3 Ready state. This link state is only used when entering the
S3/S4/S5 system power management states.
Implication: None known. No system failures have been observed. System will still enter S3/S4/S5
power management states.
Workaround: None.
Status:
NoFix. For affected steppings, see the Summary Table of Changes.
Intel® 3000 and 3010 Chipset Memory Controller Hub (MCH)
Specification Update
Order Number: 313954-004
11
INTEL [ INTEL ]
