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313072-002 参数 Datasheet PDF下载

313072-002图片预览
型号: 313072-002
PDF下载: 下载PDF文件 查看货源
内容描述: 高级内存缓冲器 [Advanced Memory Buffer]
分类和应用:
文件页数/大小: 250 页 / 3863 K
品牌: INTEL [ INTEL ]
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Transparent Mode  
10 Transparent Mode  
Figure 10-1 shows the typical architecture of a DRAM with a 4 bit wide data path. The  
memory array operates at 100 to 200 MHz. With a pre-fetch of 4, there are 4 bits of  
data on each array access, allowing us to clock data in or out at 400 MHz. This 4 to 1  
multiplexing and de-multiplexing is performed in the input register or output  
multiplexer.  
Figure 10-1. DRAM Architecture  
10.1  
Transparent Mode  
Refer to the JEDEC publication: FB-DIMM Draft Specification: Design for Test, Design  
for Validation (DFx) Specification for information regarding transparent mode.  
Transparent mode is designed to allow access to the DRAM behind the AMB. In this  
mode high speed pins are converted into low speed pins and mapped to DRAM pins.  
The objective is to allow the use of existing test equipment and manufacturing  
processes. The tester must be capable of operation at 200 MHz. Transparent mode  
offers potential improvements in test capacity over traditional DIMMs. In this mode,  
FBD requires only 60 active pins to test the DIMM.  
Intel® 6400/6402 Advanced Memory Buffer Datasheet  
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