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313072-002 参数 Datasheet PDF下载

313072-002图片预览
型号: 313072-002
PDF下载: 下载PDF文件 查看货源
内容描述: 高级内存缓冲器 [Advanced Memory Buffer]
分类和应用:
文件页数/大小: 250 页 / 3863 K
品牌: INTEL [ INTEL ]
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Transparent Mode  
10.2  
Transparent Mode Timing  
10.2.1  
Clock Frequency and Core Timing  
The DDR2 DRAM clock frequency is 200 to 400 MHz but core timings require several  
clocks (or nS) to complete.  
For example on DDR2 667:  
• tCL, tRP and tRCD are 4 clocks or 12 ns  
• tRC is 57 ns  
• tRRD is 7.5 ns  
DDR2 transactions are burst-oriented, reading or writing 4 or 8 words of data across 4  
or 8 clock edges. Assuming a 4 bit burst, a x8 DRAM will transfer 32 bits on successive  
edges of 2 DRAM clock cycles. On the tester side of the interface the same 32 bits of  
data is transferred, 16 bits at a time, over two DRAM cycles.  
10.2.2  
Edge Placement Accuracy  
Command, address and data edges should be reasonably close to the appropriate clock  
edge but with some margin of error. DRAM setup and hold times are 400 to 600 pS,  
while the half cycle time is at least 1250 pS. As long as the data is within 625 pS of the  
clock edge it will not violate setup or hold. Since there will be other error terms (DIMM  
trace length matching, jitter, and so forth) it is recommended the tester be accurate to  
±300 pS.  
During Transparent mode testing, the core clock is tied to the input reference clock by  
selecting a special mode in the PLL. Normally, the PLL uses an internal feedback loop  
for maintaining lock. In this special mode, the end of the core clock tree is fed back as  
the feedback clock to the PLL. This makes driving and receiving data at the pins of the  
chip deterministic with respect to the reference clock. This feedback mode for the PLL  
can be selected automatically in Transparent Mode.  
10.2.3  
Transparent Mode Timing  
Normally, transparent mode will use DDR2-400 timing even if the DRAM is rated for  
faster operation. Optionally an AMB may support operation at frequencies higher than  
200 MHz.  
To set up transparent mode the appropriate AMB registers should be set to AL=0, CL=4  
and CMD2DATA=4. Some AMBs may default to these values, in which case  
programming has no effect. These values establish an internal timing relationship as  
illustrated in the following figures. Optionally other register values may be supported  
for special test cases.  
Actual placement of DRAM read/write or other commands is dependent on the incoming  
signals, not the AMB register values. Figure shows an example of a write, read, write  
sequence using incoming signals that correspond to WL=4 and RL=5. The timing  
relationships in red (normal font) are fixed relationships (established by the AMB  
register settings above). These edges will move together. The relationships in green  
(italic font) are the DRAM timings, which are under control of the tester.  
102  
Intel® 6400/6402 Advanced Memory Buffer Datasheet