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313072-002 参数 Datasheet PDF下载

313072-002图片预览
型号: 313072-002
PDF下载: 下载PDF文件 查看货源
内容描述: 高级内存缓冲器 [Advanced Memory Buffer]
分类和应用:
文件页数/大小: 250 页 / 3863 K
品牌: INTEL [ INTEL ]
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Transparent Mode  
Data from the tester is 16 bits wide at 200 MHz (single data rate). The data rate is  
doubled and the width halved on the way to the DRAM (by clocking out 8 bits of data on  
the rising edge of the clock and the remaining 8 bits on the falling edge).  
The tester will drive data to be written to the DRAM on a write pass and data to be  
compared on a read. DRAM data and the expected data from the tester is compared in  
the AMB. If the actual and expected data differ the pass/fail outputs will indicate which  
DRAM failed.  
10.1.1  
Block Diagram  
The data paths for transparent mode will bypass all link logic and normal DRAM control  
logic. The DDR interfaces are used intact. Figure 10-2 is a block diagram of the Intel  
6400/6402 Advanced Memory Buffer (AMB) in transparent mode.  
Figure 10-2. Block Diagram for the AMB in transparent mode  
SET  
SET  
CLR  
D
D
Q
Q
D
Q
Q
DRAM CMD/ADD  
TCMD/TADD  
CLR  
SET  
Shift Register  
Q
Q
TDRV  
Controlled by AMB CL, AL  
or hard coded for WL=3  
ENB  
SET  
CLR  
D
Q
Q
CLR  
SET  
Multiplexer  
D
Q
Q
TDQ  
S1  
D
16  
144  
CLR  
S2  
ENB  
SET  
CLR  
D
Q
Q
C
ENB  
DFTDATA  
DRAMWR  
DRAM DQ  
DRAM DQS  
Multiplexer  
SET  
CLR  
Q
Q
D
Status  
D
S1  
DDR IO Read  
Data FIFO  
SET  
CLR  
Q
D
16  
S2  
Q
ENB  
C
ENDOUT, DRAMRD  
Read Pointer  
Shift Register  
Controlled by AMB CL, AL, CMD2DATA  
or hard coded to RL=4 and CMD2DATA=4  
SET  
CLR  
D
Q
Q
TCMP  
ENB  
10.1.2  
Transparent Mode Signal Definitions  
When the transparent mode is enabled. The FBD (Fully-Buffered DIMM) differential  
input pins designed in the AMB part become two single ended inputs. In transparent  
mode the FBD input pins require 0 to 500 mV swing (half of the normal differential  
input voltage). Input slew rates should be approximately 5 V/ns. This parameter is not  
critical, but it must be fast enough to be recognized by the AMB receiver. The DDR pins  
will operate with normal DDR2 timings and levels.  
The AMB clock input pins will be used for transparent mode as well as normal mode.  
This also allows use of most of the existing on-chip clock distribution network.  
100  
Intel® 6400/6402 Advanced Memory Buffer Datasheet