Debug and Logic Analyzer Mode
Figure 5-4. LAI Match and Mask Logic
MM_12
AND
(full frame)
Match & Mask
Registers for
Cmnd #0
OR – match
0 in any pos
MM_11
MM_2
MMEVENT[2]
13:1 mux
Mask &
match A
Cmd slot
Combining
Results
& Reg.
A matches 0
B matches 0
C matches 0
13
13
Cmd
Qual
Logic
MM_5
MM_8
Early Southbound
Pipeline stage
Mask &
match B
Cmd slot
Combining
Results
& Reg.
MMEVENT[1
13:1 mux
Match
Events
Mask &
match C
Cmd slot
Combining
Results
& Reg.
Match & Mask
Registers for
Cmnd #1
MM_10
13
OR -match 1
in any pos
A matches 1
B matches 1
C matches 1
M&M CmdA
M&M CmdB
M&M CmdC
MM_1
MM_4
MMEVENT[0
13:1 mux
Cmd
Qual
Logic
MM_7
Match & Mask
Registers for
Cmnd #2
13
OR – match MM_9
2 in any pos
A matches 2
B matches 2
C matches 2
M&M CmdA
M&M CmdB
M&M CmdC
MM_0
MM_3
MM_6
Cmd
Qual
Logic
5.1.8.2.1
Additional Qualification on Match/Mask
Full frame and A-slot matching is enabled part way through TS0, once FBD inputs have
been aligned with the core clocking phases. Though generally, will not be used until link
has completed initialization.
Slot B and Slot C pattern matching is further qualified so that true commands can be
differentiated from data when not doing full frame matching.
For each mask and match pair 0, 1 or 2
• If Mask[39] = 1, then match and mask against any received data in Slot B and Slot
C.
• If Mask[39] = 0 AND Match[39] = 0 then only match on commands.
— Ignore a match with contents of Slot B if
Frame type is not Command or
Frame type is command and A-command is Sync or Soft Reset
— Ignore a match with contents of Slot C if
Frame type is not Command or
Frame type is command and A-command is Sync or Soft Reset or
B-command is Write Configuration Register
Intel® 6400/6402 Advanced Memory Buffer Datasheet
61
INTEL [ INTEL ]
