Debug and Logic Analyzer Mode
Table 5-4.
List of Shared DDR/LAI Pins (Sheet 2 of 2)
DDR Pin
A[5:0]A
Count Speed Mbit/sec
LAI Mode
Comment
6
533/667
nbframe_data0[5:0],
[11:6]
5:0 captured on rising
edge of CLK,
11:6 captured on falling
edge of CLK
A[11:6]A
6
6
533/667
533/667
nbframe_data1[5:0],
[11:6]
BA[1:0]A,
A[15:12]A
nbframe_data2[5:0],
[11:6]
DQ[23:20], DQS[11],
DQS[11]
6
6
6
6
6
6
6
6
6
6
6
2
2
533/667
533/667
533/667
533/667
533/667
533/667
533/667
533/667
533/667
533/667
533/667
267/333 MHz
267/333 MHz
nbframe_data3[5:0],
[11:6]
DQ[31:28], DQS[12],
DQS[12]
nbframe_data4[5:0],
[11:6]
DQ[19:16], DQS[2],
DQS[2]]
nbframe_data5[5:0],
[11:6]
DQ[27:24], DQS[3],
DQS[3]
nbframe_data6[5:0],
[11:6]
DQ[15:12], DQS[10],
DQS[10]
nbframe_data7[5:0],
[11:6]
DQ[7:4], DQS[9],
DQS[9]
nbframe_data8[5:0],
[11:6]
DQ[11:8], DQS[1],
DQS[1]
nbframe_data9[5:0],
[11:6]
DQ[3:0], DQS[0],
DQS[0]
nbframe_data10[5:0],
[11:6]
CB[3:0], DQS[8],
DQS[8]
nbframe_data11[5:0],
[11:6]
CB[7:4], DQS[17],
DQS[17]
nbframe_data12[5:0],
[11:6]
DQ[63:60], DQS[16],
DQS[16]
nbframe_data13[5:0],
[11:6]
CLK[3:2]
nc
Not supported in LAI
Mode
CLK[3:2]
nc
Not supported in LAI
Mode
CLK[1:0]
2
2
267/333 MHz
267/333 MHz
LAI clock p [1:0]
LAI clock n [1:0]
CLK[1:0]#
162
No spare pins
Total DDR Pins
5.1.6
FBD to LAI Signal Mapping
The following example show how an FBD Southbound Command Frame is transferred
from FBD frame format to LA Interface early/late data.
The LAI interface delays the SB “A slot” by one clock to capture the FBD frame in the
same “ABC” slot format that is sent from the host - rather than the “BCA” (B and C slots
from host frame N-1 plus A slot from host frame N) used by the normal mode AMBs to
minimize latency on the decode of slot A commands.
58
Intel® 6400/6402 Advanced Memory Buffer Datasheet
INTEL [ INTEL ]
