Debug and Logic Analyzer Mode
Figure 5-7. Event Bus Signal Timing
Pulse EV Bus timing
Selected
Local
Event
Filtered
EVBus
Pulse Out
EVT
EVT
Received
EVBus
Signal
Filtered
EVBus
Pulse In
Local Event
Additional pulses filtered
out for period of at least
2 * EVT
Qualifier Level EV Bus timing
Selected
Local
Event
Filtered
EVBus
Pulse Out
Minimum Pulse = EVT
Received
EVBus
Signal
Filtered
EVBus
Pulse In
Local Event
Minimum Pulse = EVT
The signals will be driven or captured by four DDR I/O buffers.
Intel® 6400/6402 Advanced Memory Buffer Datasheet
65
INTEL [ INTEL ]
