DDR MemBIST
When using the built-in algorithms, the initial command for the algorithm must be
entered into MBCSR:cmd. For all algorithms except data retention read, the initial
command to enter is write (0x1). For the data retention read algorithm, the initial
command to enter is read and check (0x3).
Because the algorithm engine takes control of the MemBIST engine to carry out the
algorithm steps, a guess about the algorithm step during which the first failure
occurred can be formulated by examining the various MemBIST control registers after
MemBIST halts on error. After the operation halts, the control register values will
generally still reflect their settings when the algorithm step detected the failure.
The algorithms provided by MemBIST are specified in the following sections. The
algorithms are specified using the following notation:
^ = increasing addressing. Addresses will be counted up, starting at 0 or the user-
defined start address as appropriate.
v = decreasing addressing. Addresses will be counted down, starting at the end of the
array or from the user-defined end address, as appropriate.
w or r = Write or Read with checking of the data against the expected data.
D or I = Data or Inverted Data
number = sequence of events
( ) = back to back operations. Example: (wD, rD) will read and then write the same cell
before moving to the next cell.
11.3.4.1
Initialization Tests
Init: ^ (wD)1
This is a simple memory initialization algorithm. Data is written
to the array with incrementing addressing.
Read and check: ^(rD)1This test is used to verify memory contents. One use of this is
data retention testing. Init may be used to write known data in
the array. The tester or system can then alter an environmental
condition, or simply wait for some period of time, and then read
the array to see if the data changed.
Scan: ^(wD)1; ^(rD)2; ^ (wI)3; ^ (rI)4
The scan test writes data to the array then reads the data back.
The second half of the test writes inverted data and reads it
back. Scan is a 4N pattern, meaning test time will be 4
traversals, times the size of the array (rows * columns * banks,
also known as ‘N’) times the average time for a read or write
operation.
11.3.4.2
Memory Stress Tests
Mats+: ^(wD)1; ^(rD2, wI3); v(rI4, wD5)
The Mats+ algorithm initializes the array to a known data
background and steps through with a read-write-inverted-data
sequence. The algorithm is performed with both incrementing
and decrementing addressing. Mats+ will detect stuck at faults
and basic address decoder faults. The algorithm is order 5N.
MarchC-: ^(wD)1; ^(rD2, wI3); ^(rI4, wD5); v(rD6, wI7); v(rI8, wD9); v(rD)10
The MarchC- algorithm initializes the array to a known data
background and steps through the array in both count-up and
count-down addressing with a read-write sequence. MarchC-
tests the array decoders and basic neighboring faults. As might
Intel® 6400/6402 Advanced Memory Buffer Datasheet
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