DDR MemBIST
The simplified block diagram of Figure 11-5 below depicts the relationship between the
LFSR seed register MBLFSRSED, the MBDATA[9, 7:4] registers, and the data sent on
the CB and DQ chip pins when MemBIST executes a write command in the circular shift
or in the LFSR data modes. The LFSR seed register is the source of the data written to
the CD and DQ chip pins (and thus to the DRAMs) in both of these modes. When
MemBIST executes a read command, the data generation is the same, but the data is
not sent on the CB and DQ pins. Instead, it is used for comparison against the data
received from the DRAMs on the corresponding pins.
Figure 11-5. MemBIST Circular Shift and LFSR Data Block Diagram
MemBIST Circular Shift and LFSR Data Block Diagram
MBLFSRSED[31:0]
32
1
0
32
CRC-32
32
1
0
MBDATA9[31:0]
[30:0]
[31:0]
[15:8]
[7:0]
[31]
[31]
[31]
[31]
[31]
late_DQ_wr_data[71:64]
early_DQ_wr_data[71:64]
DDR Logic
cb[7:0]
load_lfsrseed
lfsr_mode
[0]
[0]
[0]
[0]
[31:1]
MBDATA7[31:0]
[30:0]
[31:0]
[31:0]
[31:0]
late_DQ_wr_data[63:32]
late_DQ_wr_data[31:0]
early_DQ_wr_data[63:32]
early_DQ_wr_data[31:0]
[31:1]
1
0
MBDATA6[31:0]
[30:0]
load_circseed
DDR Logic
dq[63:0]
[31:1]
MBDATA5[31:0]
[30:0]
[31:1]
MBDATA4[31:0]
[30:0]
[31:0]
MBCSR: invert
[0]
[31:1]
32
0002
In circular shift data mode, the 0 input of the mux at the far right is selected, since this
is not LFSR mode. At the beginning of MemBIST execution in this mode, the value of
the LFSR seed register is loaded into MBDATA9 by asserting the load_circseed signal
shown. Registers MBDATA[7:4] are all cleared to 0 at this time, so that their previous
contents are lost.
Each time that MemBIST execution requires data to be written to the DRAMs, 144 bits
are taken from the 160 bits comprising MBDATA[9,7:4], as shown in the figure. The
144 bits are either inverted or not before being sent to the DDR logic to be written to
the DRAMs, depending upon the state of the MBCSR:invert bit. After using the data,
the MBDATA[9,7:4] registers are clocked once, shifting the data around within these
registers to form new data to be used by MemBIST the next time that data is required.
For example, when MemBIST starts and MBCSR:invert is 0, the value from the LFSR
seed register will be loaded into MBDATA9, and MBDATA[7:4] will be cleared, so that
the first data available for MemBIST to write to the CB and DQ pins will consist of
MBDATA9[7:0] sent on the early cycle on the CB pins, MBDATA9[15:8] on the late cycle
on the CB pins, and 0s sent on all of the DQ pins on both the early and late cycles.
Once this data has been used, the MBDATA[9,7:4] registers are clocked. The data path
between the MBDATA registers is wired so that the data undergoes a left circular shift
when passing to the next register. Bits [30:0] become bits [31:1] in the receiving
register, and bit [31] becomes bit [0] in the receiving register. For example,
0x8000_0001 in MBDATA9 becomes 0x0000_0003 upon being loaded into MBDATA7.
124
Intel® 6400/6402 Advanced Memory Buffer Datasheet
INTEL [ INTEL ]
