DDR MemBIST
In LFSR data mode, a similar procedure is followed, with the exception that the
lfsr_mode signal causes the mux on the far right of the figure to select the output of
the CRC-32 block to provide the input to register MBDATA9. At the beginning of
MemBIST execution, load_lfsrseed asserts once to use the value in the LFSR seed
register as the initial input to the CRC-32 block. On subsequent register loads, the
current value in MBDATA9 is used as the input to the CRC-32 block. Each time that
MBDATA9 is loaded with a new data value from the CRC-32 block, each of MBDATA[7:4]
also load new values from their inputs.
Before the first 144 bits of data are used by MemBIST in LFSR mode, 5 register loads
occur. This fills all bits in MBDATA[9,7:4] with random data values before the first data
is written to the DRAMs.
Table 11-6 below shows an excerpt from an example run of MemBIST executing with
MBCSR:dtype = 2, circular shift data. The table illustrates the relationship between the
LFSR seed register MBLFSRSED, the BMDATA[9, 7:4] registers, and the data sent on
the CB and DQ chip pins when executing in the circular shift mode with MBCSR:invert =
0. The table also illustrates how the circular shift occurs in the MBDATA registers. This
further illustrates the process explained and shown above.
Table 11-6. Example of Circular Data Shifting
Mbdata9
xxL[71:64
]E[71:64]
Mbdata7
L[63:32]
Mbdata6
L[31:0]
Mbdata5
E[63:32]
Mbdata4
E[31:0]
Early
CB
Late
CB
#
Early DQ
Late DQ
1
2
0000_0001
0
0
0
0
0
0
0
0
01
0
0
0
0
0
0
0000_0002
0000_0002
_0000_0000
3
4
5
6
0
0
0
0
0
0000_0004
0
0
0
0
0
0
0
0
0
0000_0000
_0000_0004
0
0
0
0
0000_0008
0
0000_0008
_0000_0000
0
0
0
0
0
0
0000_0010
0
0
0000_0000
_0000_0010
0000_0020
20
0
In the example shown, MBLFSRSED contains 0x0000_0001 when MemBIST execution
starts. MBCSR contains 0x8022_0a90. Line 1 shows the data from MBLFSRSED loaded
into MBDATA9, and shows how 144 bits of the data from MBDATA[9,7:4] are sent on
the CB and DQ pins when required by MemBIST. Line 2 shows the result of the circular
shift of MBDATA9 into MBDATA7, as explained previously. Line 2 also shows how this
second set of 144 bits of data will appear on the CB and DQ pins when it is used by
MemBIST. The table shows how the original data from MBLFSRSED is transferred from
register to register each time that data is required by MemBIST execution, with a one-
bit left circular shift occurring at each register transfer. Line 6 shows the data from
MBDATA4 arriving at MBDATA9, again with a circular shift left.
Table 11-7 below shows an excerpt from an example run of MemBIST executing with
MBCSR:dtype = 3, LFSR data. The table illustrates the relationship between the LFSR
seed register MBLFSRSED, the MBDATA[9, 7:4] registers, and the data sent on the CB
and DQ chip pins when executing in the LFSR data mode. The table also illustrates how
the circular shift occurs in the MBDATA registers during LFSR data mode with
MBCSR:invert = 0. This further illustrates the process shown in the figure above.
Intel® 6400/6402 Advanced Memory Buffer Datasheet
125
INTEL [ INTEL ]
