DDR MemBIST
Table 11-7. Example of LFSR Random Data
Mbdata9
xxL[71:64
]E[71:64]
Mbdata7
L[63:32]
Mbdata6
L[31:0]
Mbdata5
E[63:32]
Mbdata4
E[31:0]
Early
CB
Late
CB
#
Early DQ
Late DQ
1
2
3
4
5
27fe_3b3d
0
0
0
0
0
0
0
0
0
0
4e2e_350c 4ffc_767a
C9a8_9bae 9c5c_6a18 9ff8_ecf4
97ca_9c36 9351_375d 38b8_d431 3ff1_d9e9
662f_8edd 2f95_386d 26a2_6ebb 7171_a862 7fe3_b3d2
4031_1dd0 cc5f_1dba 5f2a_70da 4d44_dd76 e2e3_50c4
dd
d0
8e
1d
7171_a862
_7fe3_b3d2
2f95_386d
_26a2_6ebb
6
4d44_dd76
cc5f_1dba
_ e2e3_50c4
_5f2a_70da
In the example shown, MBLFSRSED contains 0x93d7_8768 when MemBIST execution
starts. MBCSR contains 0x8011_0b90. Lines 1 through 5 show filling of
MBDATA[9,7:4] with random data generated by the CRC-32 block. For each line, newly
generated random data is loaded into MBDATA9, and MBDATA[7:4] are loaded with
data which is the result of a circular left shift from the register above it. Line 5 shows
how 144 bits of the data from MBDATA[9,7:4] is sent on the CB and DQ pins when
required by MemBIST. Line 6 shows the result of the circular shift of the contents of
each MBDATA register into the next MBDATA register. Line 6 also shows how this
second set of 144 bits of data will appear on the CB and DQ pins when it is used by
MemBIST. The table shows how the random data from MBDATA9 is transferred from
register to register each time that data is required by MemBIST execution, with a one-
bit left circular shift occurring at each register transfer.
11.3.4
Algorithmic Testing
MemBIST provides several of the more common algorithmic tests. Several of these are
directed at basic operation such as initializing memory or verifying proper connectivity
of the AMB and DRAM on a DIMM. In addition there are a few tests that are intended to
perform testing of the AMB address generators and DRAM internal address decoders,
multiplexers and related logic that is not otherwise testable at speed.
The algorithm engine takes control of the MemBIST engine to carry out the algorithm
steps. It does this by writing to some of the control bits in MBCSR. As a result, those
control bits used by the algorithm engine are not available for setting by the user.
However, the remaining control bits may be utilized by the user to control the
algorithm. The MemBIST controls which may be selected by the user when using one
of the built-in algorithms are:
• Address sequencing (Fast X, Fast Y, Fast XY, and XZY)
• Rank selection
• Halt or continue on error
When an algorithm is used, the data used for the test is always the fixed pattern 0xA.
No other pattern may be chosen. The address space for the algorithm is always the
address range specified by MB_START_ADDR and MB_END_ADDR. If testing of the full
address range of the DRAM is required, then the MB_START_ADDR and MB_END_ADDR
registers must be set to this address range.
126
Intel® 6400/6402 Advanced Memory Buffer Datasheet
INTEL [ INTEL ]
