Features
Figure 15.
Processor Low Power State Machine
HALT or MWAIT Instruction and
HALT Bus Cycle Generated
Enhanced HALT or HALT State
Normal State
Normal execution
INIT#, BINIT#, INTR, NMI, SMI#,
RESET#, FSB interrupts
BCLK running
Snoops and interrupts allowed
Snoop
Event
Occurs
Snoop
Event
Serviced
STPCLK#
Asserted
STPCLK#
De-asserted
Enhanced HALT Snoop or HALT
Snoop State
BCLK running
Service snoops to caches
Snoop Event Occurs
Snoop Event Serviced
Stop Grant State
Stop Grant Snoop State
BCLK running
BCLK running
Snoops and interrupts allowed
Service snoops to caches
6.2.1
6.2.2
Normal State
This is the normal operating state for the processor.
HALT and Enhanced HALT Powerdown States
The Celeron D processor supports the HALT or Enhanced HALT powerdown state. The
Enhanced HALT Powerdown state is configured and enabled via the BIOS. The
Enhanced HALT state must be enabled via the BIOS for the processor to remain within
its specifications.
The Enhanced HALT state is a lower power state as compared to the Stop Grant State.
If Enhanced HALT is not enabled, the default Powerdown state entered will be HALT.
Refer to the following sections for details about the HALT and Enhanced HALT states.
86
Datasheet
INTEL [ INTEL ]
